ADV7183KST Analog Devices Inc, ADV7183KST Datasheet
ADV7183KST
Specifications of ADV7183KST
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ADV7183KST Summary of contents
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ADV7183 ISO REFOUT AIN1 10-BIT ADC ANALOG I/P AIN2 MULTIPLEXING AUTOMATIC AIN3 GAIN 27MHz CONTROL AIN4 (AGC) CLAMP AND AIN5 DC RESTORE 10-BIT AIN6 ADC PWRDN HSYNC FIELD VSYNC HREF ADLLT is a trademark and ADV is a registered ...
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ADV7183–SPECIFICATIONS Parameter STATIC PERFORMANCE Resolution (each ADC) Accuracy (each ADC) 3 Integral Nonlinearity 3 Differential Nonlinearity 3 DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, V INL Input Current Input Capacitance DIGITAL OUTPUTS ...
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VIDEO PERFORMANCE SPECIFICATIONS Parameter 2 NONLINEAR SPECIFICATIONS Differential Phase Differential Gain Luma Nonlinearity 2 NOISE SPECIFICATIONS SNR (Ramp) Analog Front End Channel Crosstalk Analog Front End Channel Crosstalk LOCK TIME AND JITTER 2 SPECIFICATIONS Horizontal Lock Time Horizontal Recovery Time ...
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ADV7183 1 TIMING SPECIFICATIONS Parameter SYSTEM CLOCK AND CRYSTAL Nominal Frequency PORT SCL Clock Frequency SCL Min Pulsewidth High SCL Min Pulsewidth Low Hold Time (Start Condition Setup Time (Start ...
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SDATA SCLOCK LLC1 LLCREF LLC2 OUTPUTS P0–P19, HREF, VREF, VSYNC, HSYNC, FIELD, DV CLKIN OUTPUTS P0–P15, HREF, VREF, VSYNC, HSYNC, FIELD OUTPUTS P0–P15, HS, VS, VREF, HREF, FIELD, ...
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... Although the ADV7183 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Model ADV7183KST + 0 PIN CONFIGURATION ...
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Pin Mnemonic 1 VS/VACTIVE 2 HS/HACTIVE 3, 14 DVSSIO 4, 15 DVDDIO 5–8, 19–24, P15–P0 32, 33, 73–76 9, 31, 71 DVSS1–3 10, 30, 72 DVDD1–3 11 AFF 12 HFF/QCLK/GL 13 AEF 16 CLKIN 17, 18, 34, 35 GPO[3:0] 25 ...
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ADV7183 Pin Mnemonic 40, 47, 53, 56, AVSS 63 41, 43, 45, 57, AVSS1–6 59, 61 42, 44, 46, 58, AIN1–6 60, 62 48, 49 CAPY1–2 50 AVDD 51 REFOUT 52 CML 54, 55 CAPC1–2 RESET 64 65 ISO 66 ...
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GENERAL DESCRIPTION The ADV7183 is an integrated video decoder that automatically detects and converts a standard analog baseband television sig- nal compatible with worldwide standards NTSC or PAL into 4:2:2 or 4:1:1 component video data compatible with 16-/8-bit CCIR601/CCIR656. The ...
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ADV7183 In S-video mode there are two clamp controllers used to sepa- rately control the luminance clamping and the chrominance clamping. Also in YCrCb component input mode there are two clamp controllers used to control the luminance clamping and the ...
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LUMINANCE PROCESSING Figure 7 shows the luminance data path. The 10-bit data from the Y ADC is applied to an antialiasing low pass filter that is designed to band-limit the input video signal such that aliasing does not occur. This ...
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ADV7183 1.0 0.8 0.6 0.2 0.4 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 0.5 1.0 1.5 2.0 FREQUENCY – MHz 0 PAL NN1 PAL NN2 –10 PAL NN3 PAL W1 PAL W2 –20 PAL NN1 –30 –40 –50 –60 0 ...
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CHROMINANCE PROCESSING Figure 17 shows the chrominance data path. The 10-bit data from the Y ADC (CVBS mode) or the C ADC (S-video) is first demodulated. The demodulation is achieved by multiplying by the locally generated quadrature subcarrier, where the ...
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ADV7183 OUTPUT INTERFACE Mode Selection Overview The ADV7183 supports three output interfaces: LLC-compatible synchronous pixel interface, the CAPI interface, and the SCAPI interface. When the part is configured in the synchronous pixel interface mode, pixel and control data are output ...
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CVBS INPUT HREF DV VREF VSYNC FIELD SAV/EAV V BIT SAV/EAV H BIT SAV/EAV F BIT CVBS INPUT HREF DV VREF VSYNC FIELD SAV/EAV V BIT SAV/EAV H BIT SAV/EAV F BIT ADV7183 ...
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ADV7183 CVBS INPUT HREF DV VREF VSYNC FIELD SAV/EAV V BIT SAV/EAV H BIT SAV/EAV F BIT CVBS INPUT HREF DV VREF VSYNC FIELD SAV/EAV V BIT SAV/EAV H BIT SAV/EAV F BIT ...
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Control and Pixel Interface FIFO Modes When the ADV7183 is configured to operate in this mode, pixel data generated within the part is buffered by a 512-pixel deep FIFO. Only active video pixels and control codes are written into the ...
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ADV7183 Manual Clock Control The ADV7183 offers several output clock mode options; the output clock frequency can be set by the input video line length, a fixed 27 MHz output user-programmable value. Informa- tion on the clock ...
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SDATA SCLOCK Register Name BASIC BLOCK Input Control Video Selection Video Enhancement Control Output Control Extended Output Control General-Purpose Output Reserved FIFO Control Contrast Control Saturation Control Brightness Control Hue Control Default Value Y Default Value C Temporal Decimation Power ...
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ADV7183 Addr Register (Hex) D7 Input Control 00 VID SEL.3 VID SEL.2 VID SEL.1 VID SEL.0 INSEL.3 Video Selection 01 ASE Video Enhancement 02 Control Output Control 03 VBI EN Extended Output 04 BT656-4 Control General-Purpose 05 HL_EN Output Reserved ...
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Addr Register (Hex) D7 Color Subcarrier 24 CSMF.23 Control 2 Color Subcarrier 25 CSMF.15 Control 3 Color Subcarrier 26 CSMF.7 Control 4 Pixel Delay Control 27 SWPC Manual Clock 28 FIX27E Control 1 Manual Clock 29 CLKVAL. CLKVAL. CLKVAL. CLKVAL. ...
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ADV7183 Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting 1 INSEL[3: VID_SEL[3: ...
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Table VII. Video Enhancement Control Register (Subaddress 02) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting 1 YPM[2:0] 4 COR[1:0] RESERVED NOTES 1 Y Peaking ...
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ADV7183 Table IX. Extended Output Control Register (Subaddress 04) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting 1 RANGE RESERVED 2 DDOS[2: BT656-4 1 ...
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Table XIII. Saturation Adjust Register (Subaddress 09) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting SAT[7: Saturation Adjust. Allows ...
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ADV7183 Table XVIII. Temporal Decimation Register (Subaddress 0E) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting 1 TDE 2 TDC[1: TDR[3: ...
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Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting 2 STATUS[7: NOTES 1 Read only 2 Provides information about the internal status of ...
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ADV7183 Table XXIV. Digital Clamp Control 1 Register (Subaddress 15) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting 1 DCCO[11:8] 2 DCFE DCT[1: ...
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Table XXVII. Comb Filter Control Register (Subaddress 19) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting RESERVED CCM[1:0] 2 CCMB_AD NOTES 1 Chroma Comb ...
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ADV7183 Table XXXII. Pixel Delay Control Register (Subaddress 27) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting RESERVED 1 0 CTA[2: ...
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Table XXXVI. Auto Clock Control Register (Subaddress 2B) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting RESERVED ACLKN[2: ...
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ADV7183 Table XL. Luma Gain Control 1 Register (Subaddress 2F) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting 1 LMG[11:8] RESERVED LAGT[1: ...
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Table XLIV. Miscellaneous Gain Control Register (Subaddress 33) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting 1 PW_UPD 2 AV_AL 3 MIRE[2:0] RESERVED CKE 1 ...
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ADV7183 Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting 1 PCLK 2 PFF 3 PDV PLLCR 6 0 PVS PHVR 1 8 ...
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Table XLIX. Resample Control Register (Subaddress 44) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting RESERVED 0 FSC_INV RESERVED 0 Color Subcarrier RTCO Inversion. Allows ...
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ADV7183 Table LIII. Power-On Reset Values for MPU Registers Addr Register (Hex) BASIC BLOCK Input Control 00 Video Selection 01 Video Enhancement Control 02 Output Control 03 Extended Output Control 04 General-Purpose Output 05 Reserved 06 FIFO Control 07 Contrast ...
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Appendix BOARD DESIGN AND LAYOUT CONSIDERATIONS The ADV7183 is a highly integrated circuit containing both preci- sion analog and high-speed digital circuitry. It has been designed to minimize interference effects on the integrity of the analog circuitry by the high-speed ...
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ADV7183 AVDD 33 F AVSS AVSS DVSS DVDD 33 F DVSS AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AVSS AVSS AVSS AVSS INPUT SWITCH OVER 0.1 F 0.1 F AVSS AVSS 0.1 F 0.1 F AVSS AVSS 0.1 F DVDD DVSS ...
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OUTLINE DIMENSIONS Dimensions shown in millimeters and (inches) 80-Lead Thin Plastic Quad Flatpack [LQFP] (ST-80) 16.25 (0.6398) 15.75 (0.6201) 1.60 (0.0630) 14.05 (0.5532) MAX 13.95 (0.5492) 0.75 (0.0295) 80 0.50 (0.0197) 1 SEATING PLANE TOP VIEW (PINS DOWN) COPLANARITY 0.10 ...
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ADV7183 ...