ADV7183KST Analog Devices Inc, ADV7183KST Datasheet - Page 24

• Manufacturer Part Number: ADV7183KST
• Manufacturer: Analog Devices Inc

Specifications of ADV7183KST

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LQFP
• Pin Count: 80
• Lead Free Status / RoHS Status: Not Compliant

ADV7183
NOTES
1
2
3
4
NOTES
1
2
3
4
5
6
NOTES
1
2
3
4
5
Bit Description
FFM[4:0]
FR
AFR
FFST
Bit Description
RANGE
RESERVED
DDOS[2:0]
BT656-4
Allows the user to select the range of output values. Can be CCIR601-compliant or fill the whole accessible number range.
D Data Output Selection. If the 100-pin package is used, the 12 additional pins can output additional data.
12 Pins Three-State
Allows the user to select an output mode that is compatible with BT656-4 or BT656-3.
Pixel Data Valid Off. These general-purpose output pins may be programmed by the user but are only available in selected output modes OF_SEL[3:0] and when the
General Purpose Enable Low. Enables the output drivers for the general-purpose outputs Bits 0 and 1.
General Purpose Enable High. Enables the output drivers for the general-purpose outputs Bits 2 and 3.
Blank Chroma During VBI.
Hlock Enable. This bit causes the GPO[0] pin to output Hlock instead of GPO[0]. Only available in certain output modes.
GPO lower bits must be enabled GPEL. Disabled.
FIFO Flag Margin. Allows the user to program the location at which the FIFO flags AEF and AFF.
FIFO Reset. Setting this bit will cause the FIFO to reset.
Bit is auto cleared.
Automatic FIFO Reset. Setting this bit will cause the FIFO to automatically reset at the end of each field of video.
FIFO Flag Self Time. Sets whether the FIFO flags AEF, AFF, and HFF are output synchronous to the external CLKIN of the 27 MHz internal clock.
output drivers are enabled using GPEL, GPEH, and HL_Enable bits.
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
CON[7:0]
Contrast Adjust. This is the user control for contrast adjustment.
Bit Description
GPO[3:0]
GPEL
GPEH
BL_C_VBI
HL_EN
2
4
5
2
3
1
5
4
1
1
2
4
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
0
1
0
1
1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
0
1
0
1
0
0
0
1
0
1
0
0
Table IX. Extended Output Control Register (Subaddress 04)
1
1
Table X. General-Purpose Output Register (Subaddress 05)
Table XI. FIFO Control Register (Subaddress 07)
0
0
0
0
0
Table XII. Contrast Register (Subaddress 08)
0
1
0
0
1
1
0
0
0
0
0
0
0
0
1
0
0
User Programmable
Normal Operation
FIFO Reset
No Auto Reset
Auto Reset
Synchronous to CLKIN
Synchronous to 27 MHz
CCIR-Compliant
Fill Whole Accessible Range
No Additional Data
BT656-3-Compatible
BT656-4-Compatible
User Programmable
HD Test Pattern Off
GPO[1:0] Three-Stated
GPO[1:0] Enabled
GPO[3:2] Three-Stated
GPO[3:2] Enabled
Decode and Output Color During VBI
Blank Cr and Cb Data During VBI
GPO[0] Pin Function
GPO[0] Shows HLOCK Status
3
3
6
6