ADV7312KST Analog Devices Inc, ADV7312KST Datasheet - Page 31

• Manufacturer Part Number: ADV7312KST
• Manufacturer: Analog Devices Inc

Specifications of ADV7312KST

• Number Of Dac's: 6
• Adc/dac Resolution: 11b
• Screening Level: Commercial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Not Compliant

If in simultaneous SD/HD input mode the two clock phases
differ by less than 9.25 ns or more than 27.75 ns, the CLOCK
ALIGN bit [Address 01h Bit 3] must be set accordingly. If the
application uses the same clock source for both SD and PS, the
CLOCK ALIGN bit must be set since the phase difference
between both inputs is less than 9.25 ns.
Progressive Scan at 27 MHz (Dual Edge) or 54 MHz
Address[01h] : Input Mode 100 or 111, Respectively
YCrCb progressive scan data can be input at 27 MHz or 54 MHz.
The input data is interleaved onto a single 8-bit bus and is input
on Pins Y7–Y0. When a 27 MHz clock is supplied, the data is
clocked in on the rising and falling edge of the input clock and
CLOCK EDGE [Address 0x01, Bit 1] must be set accordingly.
The following figures show the possible conditions: (a) Cb data
on the rising edge and (b) Y data on the rising edge.
REV. 0
CLKIN_A
CLKIN_B
CLKIN_B
CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 0 IN THIS CASE.
Y7–Y0
Figure 26a. Input Sequence in PS Bit Interleaved
Mode (EAV/SAV)
Figure 25. Clock Phase with Two Input Clocks
t
t
DELAY
DELAY
3FF
9.25ns OR
27.75ns
00
00
XY
Cb0
Y0
Cr0
Y1
–31–
Table I provides an overview of all possible input configurations.
PIXEL INPUT
WITH A 54 MHz CLOCK, THE DATA IS LATCHED ON EVERY RISING EDGE.
CLKIN_B
CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 1 IN THIS CASE.
Y7–Y0
Figure 26b. Input Sequence in PS Bit Interleaved
Mode (EAV/SAV)
CLKIN
Figure 26c. Input Sequence in PS Bit Interleaved
Mode (EAV/SAV)
DATA
Figure 27. 1
3FF
PROGRESSIVE
DECODER
INTERLACED
MPEG2
3FF
YCrCb
TO
00
00
27MHz OR 54MHz
8-Bit PS at 27 MHz or 54 MHz
00
YCrCb
00
XY
XY
8
3
Y0
CLKIN_A
Y[7:0]
P_VSYNC
P_HSYNC
P_BLANK
Cb0
ADV7312
Cb0
ADV7312
Y0
Y1
Cr0
Cr0
Y1