ADV7312KST Analog Devices Inc, ADV7312KST Datasheet - Page 6

• Manufacturer Part Number: ADV7312KST
• Manufacturer: Analog Devices Inc

Specifications of ADV7312KST

• Number Of Dac's: 6
• Adc/dac Resolution: 11b
• Screening Level: Commercial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Not Compliant

ADV7312
TIMING SPECIFICATIONS
R
Parameter
MPU PORT
ANALOG OUTPUTS
CLOCK CONTROL AND PIXEL PORT
PIPELINE DELAY
NOTES
1
2
3
4
Specifications subject to change without notice.
Guaranteed by characterization.
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.
Data: C[7:0]; Y[7:0], S[7:0]
SD, PS = 27 MHz, HD = 74.25 MHz.
Control: P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, S_VSYNC, S_BLANK.
LOAD
SCLOCK Frequency
SCLOCK High Pulsewidth, t
SCLOCK Low Pulsewidth, t
Hold Time (Start Condition), t
Setup Time (Start Condition), t
Data Setup Time, t
SDATA, SCLOCK Rise Time, t
SDATA, SCLOCK Fall Time, t
Setup Time (Stop Condition), t
RESET Low Time
Analog Output Delay
Output Skew
f
f
Clock High Time, t
Clock Low Time, t
Data Setup Time, t
Data Hold Time, t
SD Output Access Time, t
SD Output Hold Time, t
HD Output Access Time, t
HD Output Hold Time, t
CLK
CLK
= 300
1
. All specifications T
4
12
10
5
11
9
1
1
2
14
14
13
13
2
1
MIN
3
8
4
7
to T
6
MAX
(V
AA
(0 C to 70 C), unless otherwise noted.)
= 2.375 V–2.625 V, V
3
Min
0
0.6
1.3
0.6
0.6
100
0.6
100
40
40
2.0
2.0
5.0
5.0
Typ
7
1
81
63
76
35
41
36
DD
–6–
= 2.375 V–2.625 V; V
Max
400
300
300
27
15
14
Unit
µs
µs
µs
µs
µs
ns
kHz
ns
ns
ns
ns
ns
MHz
MHz
% of one clk cycle
% of one clk cycle
ns
ns
ns
ns
ns
ns
clk cycles
clk cycles
clk cycles
clk cycles
clk cycles
DD_IO
= 2.375 V–3.6 V, V
Test Conditions
First clock generated after this period
relevant for repeated start condition
Progressive scan mode
HDTV mode/async mode
SD [2 , 16 ]
SD component mode [16 ]
PS [1 ]
PS [8 ]
HD [2 , 1 ]
REF
= 1.235 V, R
SET
= 3040
REV. 0
,