SAA7154E/V2/G NXP Semiconductors, SAA7154E/V2/G Datasheet - Page 13

• Manufacturer Part Number: SAA7154E/V2/G
• Manufacturer: NXP Semiconductors

Specifications of SAA7154E/V2/G

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SAA7154E_SAA7154H_2
Product data sheet
Table 4.
Symbol
XRDY
XRH
XRV
XTRI
Host port (H-port; see
HPD7
HPD6
HPD5
HPD4
HPD3
HPD2
HPD1
HPD0
Real-time clock (see
RTCO
RTS1
RTS0
Clocks (see
LLC
LLC2_54
XTALI
XTALO
XTOUT
Boundary scan test
TCK
TDI
Pin description
Pin
QFP160 LBGA156
146
141
140
126
103
105
107
109
110
111
112
113
71
70
69
46
48
155
156
158
148
152
Section
7.14.3)
Section 7.14.3
A6
C7
D8
B11
G13
F14
F13
E14
E12
E13
E11
D14
L10
N10
M10
P4
N5
B4
A3
A2
B6
B5
Rev. 02 — 6 December 2007
Section
…continued
7.14.4.1)
Type
O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O/st/pd real-time control output; contains information about
O
O
O
O
I
O
O
I/pu
I/pu
and
[1]
Section
Description
task flag or ready signal from scaler, I
controlled
horizontal reference I/O expansion port
vertical reference I/O expansion port
X-port output control signal, affects all X-port pins
(XPD7 to XPD0, XRH, XRV, XDQ and XCLK), enable
and active polarity is under software control
MSB of host port data I/O, extended C
expansion port, extended C
bit 6 of host port data I/O, extended C
expansion port, extended C
bit 5 of host port data I/O, extended C
expansion port, extended C
bit 4 of host port data I/O, extended C
expansion port, extended C
bit 3 of host port data I/O, extended C
expansion port, extended C
bit 2 of host port data I/O, extended C
expansion port, extended C
bit 1 of host port data I/O, extended C
expansion port, extended C
LSB of host port data I/O, extended C
expansion port, extended C
actual system clock frequency, field rate, odd/even
sequence, decoder status, subcarrier frequency and
phase and PAL sequence
real-time status or sync information, controlled by
subaddresses 11h and 12h
real-time status or sync information, controlled by
subaddresses 11h and 12h
line-locked system clock output (27 MHz nominal)
line-locked
ADC clock 54 MHz, selectable through I
input terminal for 24.576 MHz (32.11 MHz) crystal
oscillator or connection of external oscillator
24.576 MHz (32.11 MHz) crystal oscillator output; do
not connect if clock input XTALI is used
crystal oscillator output signal; auxiliary signal
test clock for boundary scan test
test data input for boundary scan test
SAA7154E; SAA7154H
Multistandard video decoder with comb filter
7.14.4.2)
1
2
clock output (13.5 MHz nominal) or
[2][4]
B
B
B
B
B
B
B
B
-C
-C
-C
-C
-C
-C
-C
-C
R
R
R
R
R
R
R
R
[5]
output for image port
output for image port
output for image port
output for image port
output for image port
output for image port
output for image port
output for image port
© NXP B.V. 2007. All rights reserved.
[5]
2
B
B
B
B
B
B
B
B
C-bus
-C
-C
-C
-C
-C
-C
-C
-C
2
C-bus
R
R
R
R
R
R
R
R
input for
input for
input for
input for
input for
input for
input for
input for
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