SAA7154E/V2/G NXP Semiconductors, SAA7154E/V2/G Datasheet - Page 41

• Manufacturer Part Number: SAA7154E/V2/G
• Manufacturer: NXP Semiconductors

Specifications of SAA7154E/V2/G

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SAA7154E_SAA7154H_2
Product data sheet
7.14.4.4 X-port configured as input
7.14.5.1 Image port
7.14.5 Image port and digital OSD
If data input mode is selected at the expansion port, then the scaler can choose its input
data stream from the on-chip video decoder or from the expansion port (controlled by bits
SCSRC[1:0]). Byte serial or 16-bit wide Y-C
schemes or raw samples from an external ADC may be input (bits FSC[2:0]; see
Table
pixelwise switching between video from the decoder and expansion port (X-port) input is
also used (special configuration controlled by XPE).
As the output configuration (8-bit, 16-bit or 24-bit) has priority and controls the H-port
enable, 16-bit input is only supported for 8-bit wide output through the I-port.
The input stream must be accompanied by an external clock (pin XCLK), qualifier XDQ
and reference signals XRH and XRV. Instead of the reference signal, embedded
SAV and EAV codes according to ITU-656 are also accepted. The protection bits are not
evaluated.
For using the raster generator or PLL2 on the X-port input stream the pins XRH and XRV
must be applied with sync signals.
The Image port (I-port) transfers data from the scaler as well as from the VBI data slicer, if
selected (maximum 54 MHz). The reference clock is available at the ICLK pin, as an
output or as an input (maximum 54 MHz). As output, ICLK is derived from the line-locked
decoder, 2nd PLL or expansion port input clock. The data stream from the scaler output is
normally discontinuous. Therefore valid data during a clock cycle is accompanied by a
data qualifying (data valid) flag on pin IDQ. In the so called DMSD2-legacy mode
(ICKS[3:2] = 10b) the IDQ pin carries a gated clock signal.
The data formats at the image port are defined in double pixel double words, such as the
related internal FIFO structures. However, the physical data stream at the image port is
only 24-bit, 16-bit or 8-bit wide. In 16-bit mode, data pins HPD[7:0] are used for
chrominance data. In 24-bit mode, pins IPD[7:0], IXD[7:0] and HPD[7:0] can be used to
output Y-C
Available formats are as follows:
For handshake with the receiving VGA controller or other memory or bus interface
circuitry, F, H and V reference signals and programmable FIFO flags are provided. The
information is provided on pins IGP0, IGP1, IGPH and IGPV. I
functionality of these pins.
•
•
•
•
•
•
Y-C
Y-C
Y-C
R-G-B 4 : 4 : 4 with 24-bit
Raw samples
Decoded VBI data.
17), where the H-port serves as the port for the chrominance input path. Optionally,
B
B
B
-C
-C
-C
B
R
R
R
-C
4 : 2 : 2 with 8-bit or 16-bit
4 : 1 : 1 with 8-bit
4 : 4 : 4 with 24-bit
R
4 : 4 : 4 or R-G-B 4 : 4 : 4 data.
Rev. 02 — 6 December 2007
SAA7154E; SAA7154H
Multistandard video decoder with comb filter
B
-C
R
4 : 2 : 2 or subsets for other sampling
2
C-bus registers control the
© NXP B.V. 2007. All rights reserved.
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