ADV7196AKS Analog Devices Inc, ADV7196AKS Datasheet
ADV7196AKS
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ADV7196AKS Summary of contents
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GENERAL DESCRIPTION The ADV7196A is a triple high-speed, digital-to-analog encoder on a single monolithic chip. It consists of three high-speed video D/A converters with TTL-compatible inputs registered trademark of Philips Corporation. Multiformat Progressive Scan/HDTV ...
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ADV7196A FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ...
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ADAPTIVE FILTER GAIN AFG3 (AFG3)7– ...
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ADV7196A–SPECIFICATIONS (V AA 3.3 V SPECIFICATIONS ( unless otherwise noted.) Parameter STATIC PERFORMANCE Resolution (Each DAC) Integral Nonlinearity Differential Nonlinearity DIGITAL OUTPUTS Output High Voltage Output Low Voltage Three State Leakage Current ...
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V TIMING–SPECIFICATIONS P arameter 1 MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth SCLOCK Low Pulsewidth Hold Time (Start Condition Setup Time (Start Condition Data Setup Time SDATA, SCLOCK Rise ...
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ADV7196A CLOCK PIXEL INPUT DATA t 11 CLOCK PIXEL INPUT DATA t 11 CLOCK PIXEL INPUT Cb0 DATA • • • • • • • • • ...
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HSYNC VSYNC A DV PIXEL DATA CLKCYCLES (525P) MIN CLKCYCLES (625P) MIN CLKCYCLES (1080I) MIN CLKCYCLES (720P) MIN t 3 SDA SCL t 2 ...
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... OUT Model Temperature Range ADV7196AKS 0°C to 70°C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7196A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges ...
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Pin Mnemonic Input/Output 2–11 Y0–Y9 I 13, 52 GND G 14–23 Cr0–Cr9 I 24 CLKIN I 26, 33 AGND VSYNC TSYNC HSYNC ...
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ADV7196A FUNCTIONAL DESCRIPTION Digital Inputs The digital inputs of the ADV7196A are TTL compatible. 30-bit YCrCb or RGB pixel data in 4:4:4 format or 20-bit YCrCb pixel data in 4:2:2 format is latched into the device on the rising edge ...
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Input/Output Configuration Table I shows possible input/output configurations when using the ADV7196A. Table I. Input Format YCrCb Progressive Scan 4:2:2 4:4:4 YCrCb HDTV 4:2:2 4:4:4 RGB Progressive Scan 4:4:4 RGB HDTV 4:4:4 Async Timing Mode All Inputs 10 0 –10 ...
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ADV7196A A Logic “0” on the LSB of the first byte means that the master will write information to the peripheral. A Logic “1” on the LSB of the first byte means that the master will read information from the ...
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REGISTER PROGRAMMING The following section describes the functionality of each register. All registers can be read from as well as written to unless other- wise stated. Subaddress Register (SR7–SR0) The Communications Register is an eight bit write-only register. After the ...
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ADV7196A PROGRESSIVE SCAN MODE MODE REGISTER 0 MR0 (MR07–MR00) (Address (SR4–SR0) = 00H) Figure 16 shows the various operations under the control of Mode Register 0. MR0 BIT DESCRIPTION Output Standard Selection (MR00–MR01) These bits are used to select the ...
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Table II must be followed when programming the control sig- nals in Async Timing Mode. Table II. Truth Table SYNC TSYNC DV 1 –> 50% Point of Falling Edge of Tri-Level Horizontal Sync Signal, A ...
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ADV7196A MODE REGISTER 1 MR1 (MR17–MR10) (Address (SR4–SR0) = 01H) Figure 20 shows the various operations under the control of Mode Register 1. MR1 BIT DESCRIPTION Pixel Data Enable (MR10) When this bit is set to “0,” the pixel data ...
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MODE REGISTER 2 MR1 (MR27–MR20) (Address (SR4–SR0) = 02H) Figure 22 shows the various operations under the control of Mode Register 2. MR2 BIT DESCRIPTION Y Delay (MR20–MR22) This control bit delays the Y signal with respect to the falling ...
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ADV7196A MODE REGISTER 3 MR3 (MR37–MR30) (Address (SR4–SR0) = 03H) Figure 23 shows the various operations under the control of Mode Register 3. MR3 BIT DESCRIPTION HDTV Enable (MR30) When this bit is set to “1” the ADV7196A reverts to ...
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MR57 ADAPTIVE MODE CONTROL MR56 0 1 ADAPTIVE FILTER CONTROL MR57 0 DISABLE 1 ENABLE Color Output Swap (MR53) By default DAC B is configured as the Pr output and DAC C as the Pb output. In setting this bit ...
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ADV7196A The Table IV shows sample color values to be programmed into the color registers when Output Standard Selection is set to EIA-770.2 (MR01–00 = “00”) . Table IV. Sample Color Values for EIA 770.2 Output n Standard Selectio Sample ...
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FILTER GAIN FG (FG7–FG0) (Address (SR4–SR0) = 10H) Figure 34 shows the various operations under the control of the Filter Gain register . FG7 FG6 FG5 FG4 FG3 FG7–FG4 FILTER GAIN B 0000 0 0001 1 0010 2 0011 3 ...
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ADV7196A 300 GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT FOR VARIOUS GAMMA VALUES 250 SIGNAL OUTPUTS 200 0.3 0.5 150 100 1.5 1 100 150 LOCATION The gamma curves shown above are examples only, any ...
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ADAPTIVE FILTER GAIN 1 AFG1 (AFG1)7–0 (Address (SR5–SR0) = 22H) This 8-bit-wide register is used to program the gain applied to signals which lie above Adaptive Filter Threshold A but are smaller than Adaptive Filter Threshold B. Gain A and ...
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ADV7196A SHARPNESS FILTER AND ADAPTIVE FILTER APPLICATION EXAMPLES Sharpness Filter Application The sharpness filter can be used to enhance or attenuate the Y video output signal. The following register settings were used to achieve the results shown in the figures ...
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In toggling MR17 (Sharpness Filter Enable/Disable) and setting the Filter Gain register value to 99hex it can be seen that the line contours of the cross hatch pattern change their sharpness Adaptive Filter Control Application The figure below shows a ...
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ADV7196A HDTV MODE MODE REGISTER 0 MR0 (MR07–MR00) (Address (SR4–SR0) = 00H) Figure 50 shows the various operations under the control of Mode Register 0. HEXMR0 BIT DESCRIPTION Output Standard Selection (MR00–MR01) These bits are used to select the output ...
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MODE REGISTER 1 MR1 (MR17–MR10) (Address (SR4-SR0) = 01H) Figure 51 shows the various operations under the control of Mode Register 1. MR1 BIT DESCRIPTION Pixel Data Enable (MR10) When this bit is set to “0,” the pixel data input ...
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ADV7196A MODE REGISTER 2 MR1 (MR27–MR20) (Address (SR4–SR0) = 02H) Figure 53 shows the various operations under the control of Mode Register 2. MR2 BIT DESCRIPTION Y Delay (MR20–MR22) With these bits it is possible to delay the Y signal ...
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MODE REGISTER 4 MR4 (MR47–MR40) (Address (SR4–SR0) = 04H) Figure 55 shows the various operations under the control of Mode Register 4. MR4 BIT DESCRIPTION Timing Reset (MR40) Toggling MR40 from low to high and low again resets the inter- ...
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ADV7196A DAC TERMINATION AND LAYOUT CONSIDERATIONS Voltage Reference The ADV7196A contains an on-board voltage reference. The through a 0.1 µF capacitor V pin is normally terminated to V REF AA when the internal V is used. Alternatively, the ADV7196A REF ...
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DAC output traces on a PCB should be treated as transmission lines recommended that the DACs be placed as close as possible to the output connector, with the analog output traces being as short as possible (less than ...
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ADV7196A An optional analog reconstruction LPF might be required as an antialias filter if the ADV7196A is connected to a device that requires this filtering. The Eval ADV7196A/7EB evaluation board uses the ML6426 Microlinear IC, which provides buffering and low-pass ...
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INPUT CODE EIA-770.2, STANDARD FOR Y 940 ACTIVE VIDEO 64 EIA-770.2, STANDARD FORPr/Pb 960 ACTIVE VIDEO 512 64 INPUT CODE EIA-770.1, STANDARD FOR Y 940 ACTIVE VIDEO 64 EIA-770.1, STANDARD FORPr/Pb 960 ACTIVE 512 VIDEO 64 INPUT CODE EIA-770.3, STANDARD ...
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ADV7196A SMPTE293M ANALOG WAVEFORM EAV CODE INPUT PIXELS 4 CLOCK SAMPLE NUMBER 719 SMPTE274M ANALOG WAVEFORM EAV CODE F INPUT PIXELS F 4 CLOCK SAMPLE NUMBER 2112 ANCILLARY DATA (OPTIONAL 723 ...
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ACTIVE VIDEO 522 523 524 525 ACTIVE VIDEO 622 623 624 625 VERTICAL BLANKING INTERVAL 747 748 749 750 1 2 FIELD 1 1124 1125 1 2 FIELD 2 561 562 563 564 VERTICAL ...
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ADV7196A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 52-Lead Plastic Quad Flatpack (MQFP) (S-52) 0.557 (14.15) 0.094 (2.39) 0.537 (13.65) 0.084 (2.13) 0.398 (10.11) 0.390 (9.91) 0.037 (0.95) 0.026 (0.65 PIN 1 SEATING PLANE TOP ...