ADV7196AKS Analog Devices Inc, ADV7196AKS Datasheet - Page 14

• Manufacturer Part Number: ADV7196AKS
• Manufacturer: Analog Devices Inc

Specifications of ADV7196AKS

• Adc/dac Resolution: 11b
• Screening Level: Commercial
• Package Type: MQFP
• Pin Count: 52
• Lead Free Status / RoHS Status: Not Compliant

ADV7196A
PROGRESSIVE SCAN MODE
MODE REGISTER 0
MR0 (MR07–MR00)
(Address (SR4–SR0) = 00H)
Figure 16 shows the various operations under the control of
Mode Register 0.
MR0 BIT DESCRIPTION
Output Standard Selection (MR00–MR01)
These bits are used to select the output levels for the ADV7196A.
If EIA-770.2 (MR01–00 = “00”) is selected the output levels will
be: 0 mV for blanking level, 700 mV for peak white for the Y
channel, ±350 mV for Pr, Pb outputs and –300 mV for Sync. Sync
insertion on the Pr, Pb channels is optional.
If EIA-770.1 (MR01–00 = “01”) is selected the output levels will
be: 0 mV for blanking level, 714 mV for peak white for the Y chan-
nel, ± 350 mV for Pr, Pb outputs and –286 mV for Sync. Optional
sync insertion on the Pr, Pb channels is not possible.
If Full I/P Range (MR01–00 = “10”) is selected the output levels
will be 0 mV for blanking level, 700 mV for peak white for the Y
channel, ±350 mV for Pr, Pb outputs and –300 mV for Sync. Sync
insertion on the Pr, Pb channels is optional. This mode is used
for RS-170, RS-343A standard output compatibility. Refer to
Appendix for output level plots.
MR07
0
1
MACROVISION
MR07
DISABLED
ENABLED
MR06
0
1
DV POLARITY
MR06
ACTIVE HIGH
ACTIVE LOW
BE WRITTEN
ZERO MUST
TO THIS BIT
MR05
MR05
MR04
0
1
INPUT STANDARD
MR04
525P
625P
Input Control Signals (MR02–MR03)
These control bits are used to select whether data is input with
external horizontal, vertical and blanking sync signals or if the data
is input with embedded EAV/SAV codes.
An Asynchronous timing mode is also available using TSYNC,
SYNC and DV as input control signals. These control signals
have to be programmed by the user.
Figure 17 shows an example of how to program the ADV7196A to
accept a different high definition standard but SMPTE293M,
SMPTE274M, SMPTE296M or ITU-R.BT1358 standard.
Input Standard (MR04)
Select between 525p progressive scan input or 625p progressive
scan input.
Reserved (MR05)
A “0” must be written to this bit.
DV Polarity (MR06)
This control bit allows to select the polarity of the DV input
control signal to be either active high or active low. This is in
order to facilitate interfacing from I to P Converters which use
an active low blanking signal output.
Macrovision (MR07)
To enable Macrovision this bit must be set to “1.”
MR03
MR03 MR02
0
0
1
1
INPUT CONTROL SIGNALS
MR01 MR00
0
0
1
1
MR02
OUTPUT STANDARD SELECTION
0
1
0
1
0
1
0
1
HSYNC\VSYNC/DV
EAV/SAV
TSYNC/SYND/DV
RESERVED
MR01
EIA-770.2
EIA-770.1
FULL I/P RANGE
RESERVED
MR00