ADV7196AKS Analog Devices Inc, ADV7196AKS Datasheet - Page 12

• Manufacturer Part Number: ADV7196AKS
• Manufacturer: Analog Devices Inc

Specifications of ADV7196AKS

• Adc/dac Resolution: 11b
• Screening Level: Commercial
• Package Type: MQFP
• Pin Count: 52
• Lead Free Status / RoHS Status: Not Compliant

ADV7196A
A Logic “0” on the LSB of the first byte means that the master will
write information to the peripheral. A Logic “1” on the LSB of
the first byte means that the master will read information from
the peripheral.
The ADV7196A acts as a standard slave device on the bus. The
data on the SDA pin is 8 bits long supporting the 7-bit addresses plus
the R/W bit. It interprets the first byte as the device address and
the second byte as the starting subaddress. The subaddresses auto-
increment allowing data to be written to or read from the starting
subaddress. A data transfer is always terminated by a Stop con-
dition. The user can also access any unique subaddress register
on a one by one basis without having to update all the registers.
Stop and Start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, then these cause an immedi-
ate jump to the idle condition. During a given SCL high period
the user should only issue one Start condition, one Stop condition
or a single Stop condition followed by a single Start condition.
If an invalid subaddress is issued by the user, the ADV7196A will
not issue an acknowledge and will return to the idle condition. If
in autoincrement mode, the user exceeds the highest subaddress
then the following action will be taken:
1. In Read Mode, the highest subaddress register contents will
continue to be output until the master device issues a no-
acknowledge. This indicates the end of a read. A no-acknowledge
condition is where the SDA line is not pulled low on the
ninth pulse.
SEQUENCE
SEQUENCE
WRITE
READ
S
S
S = START BIT
P = STOP BIT
SLAVE ADDR A(S)
SLAVE ADDR A(S)
LSB = 0
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
SUB ADDR
SUB ADDR
A(S)
A(S) S SLAVE ADDR A(S)
DATA
2. In Write Mode, the data for the invalid byte will be not be
Figure 12 illustrates an example of data transfer for a read
sequence and the Start and Stop conditions.
Figure 13 shows bus write and read sequences.
REGISTER ACCESSES
The MPU can write to or read from all of the registers of the
ADV7196A except the Subaddress Registers, which are write-only
registers. The Subaddress Register determines which register the
next read or write operation accesses.
All communications with the part through the bus begin with an
access to the Subaddress Register. A read/write operation is per-
formed from/to the target address which then increments to the
next address until a Stop command on the bus is performed.
SCLOCK
LSB = 1
A(S)
SDATA
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7196A and the part will return to the
idle condition.
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
START ADDR R/W ACK SUBADDRESS ACK
S
DATA
1
–
7
DATA
8
A(M)
9
A(S) P
1
–
7
8
DATA
9
A(M)
DATA
1
–
7
P
8
ACK
9
STOP
P