NE5537N NXP Semiconductors, NE5537N Datasheet - Page 2

• Manufacturer Part Number: NE5537N
• Manufacturer: NXP Semiconductors

Specifications of NE5537N

• Number Of Sample And Hold Elements: 1
• Power Supply Requirement: Dual
• Single Supply Voltage (typ): Not RequiredV
• Single Supply Voltage (min): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Package Type: PDIP
• Lead Free Status / RoHS Status: Compliant

is pin-compatible with the LF198, and features superior performance
Philips Semiconductors
DESCRIPTION
The NE5537 monolithic sample-and-hold amplifier combines the
best features of ion-implanted JFETs with bipolar devices to obtain
high accuracy, fast acquisition time, and low droop rate. This device
in droop rate and output drive capability. The circuit shown in
Figure 5 contains two operational amplifiers which function as a
unity gain amplifier in the sample mode. The first amplifier has
bipolar input transistors which give the system a low offset voltage.
The second amplifier has JFET input transistors to achieve low
leakage current from the hold capacitor. A unique circuit design for
leakage current cancellation using current mirrors gives the NE5537
a low droop rate at higher temperature. The output stage has the
capability to drive a 2 k load. The logic input is compatible with
TTL, PMOS or CMOS logic. The differential logic threshold is 1.4 V
with the sample mode occurring when the logic input is high. It is
available in 8-pin plastic DIP and 14-pin SO packages.
FEATURES
ORDERING INFORMATION
2001 Aug 03
8-Pin Plastic Dual In-Line Package (DIP)
14-Pin Plastic Small Outline (SO) Package
Operates from 5 V to 18 V supplies
Hold leakage current 6 pA @ T
Less than 4 s acquisition time
TTL, PMOS, CMOS compatible logic input
0.5 mV typical hold step at C
Low input offset: 1 MV (typical)
0.002% gain accuracy with R
Low output noise in hold mode
Input characteristics do not change during hold mode
High supply rejection ratio in sample or hold
Wide bandwidth
Sample-and-hold amplifier
DESCRIPTION
H
L
= 0.01 F
= 2 k
j
= 25 C
2
PIN CONFIGURATIONS
BLOCK DIAGRAM
LOGIC
REFERENCE
TEMPERATURE RANGE
LOGIC
NOTE:
1. SO and non-standard pinouts.
INPUT
0 C to +70 C
0 C to +70 C
OFFSET ADJUST
3
8
7
OUTPUT
–
+
–
+
OFFSET
INPUT
INPUT
Figure 1. Pin Configuration
Figure 2. Block Diagram
NC
NC
NC
NC
V+
V–
V–
2
1
2
3
4
1
2
3
4
5
6
7
N Package
D
1
Package
ORDER CODE
30 k
NE5537N
NE5537D
14
13
12
11
10
9
8
8
7
6
5
HOLD
CAPACITOR
LOGIC
LOGIC REFERENCE
OUTPUT
NC
V+
LOGIC
LOGIC REFERENCE
NC
C
C
V
h
h
OS
6
300
ADJ
853-1044 26836
SL00342
NE5537
Product data
SOT108-1
SOT97-1
DWG #
SL00343
5
OUTPUT