NE5537N NXP Semiconductors, NE5537N Datasheet - Page 6

• Manufacturer Part Number: NE5537N
• Manufacturer: NXP Semiconductors

Specifications of NE5537N

• Number Of Sample And Hold Elements: 1
• Power Supply Requirement: Dual
• Single Supply Voltage (typ): Not RequiredV
• Single Supply Voltage (min): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Package Type: PDIP
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
SAMPLE-AND-HOLD
For many years designers have used the sample-and-hold (or
track-and-hold) to operate on analog information in a time frame
which is expedient.
By sampling a segment of the information and holding it until the
proper timing for converting to some form of control signal or
readout, the designer maintains certain freedom in performing
predetermined manipulative functions. Therefore, the
sample-and-hold can be defined as a “selective analog memory
cell”.
The memory is volatile and will also decay with time.
When using the sample-and-hold method for evaluating signal
information, the designer is given the added feature of eliminating
outside noise elements. With the analog-to-digital converter
products available today, the “DC memory” of the sample-and-hold
can be easily converted to digital format and further incorporated
into microprocessor-based systems.
Parametric evaluation of the sample-and-hold will be discussed in
the following paragraphs.
DEFINITION OF TERMS
Acquisition Time — The time required to acquire a new analog
input voltage with an output step of 10 V. Note that acquisition time
is not just the time required for the output to settle, but also includes
the time required for all internal nodes to settle so that the output
assumes the proper value when switched to the hold mode.
Aperture Delay Time — The time elapsed from the hold command
to the opening of the switch.
Aperture Jitter — Also called “aperture uncertainty time”, it is the
time variation or uncertainty with which the switch opens, or the time
variation in aperture delay.
Aperture Time — The delay required between “HOLD” command
and an input analog transition, so that the transition does not affect
the held output.
Bandwidth — The frequency at which the gain is down 3 dB from
its DC value. It’s measured in sample (track) mode with a
small-signal sine wave that doesn’t exceed the slew rate limit.
Dynamic Sampling Error — The error introduced into the hold
output due to a changing analog input at the time the hold command
is given. Error is expressed in mV with a given hold capacitor value
and input slew rate. Note that this error term occurs even for long
sample times.
Effective Aperture Delay — The time difference between the hold
command and the time at which the input signal is at the held
voltage.
Figure of Merit — The ratio of the available charging current during
sample mode to the leakage current during hold mode.
Gain Error — The ratio of output voltage swing to input voltage
swing in the sample mode expressed as a percent difference.
Hold Mode Droop — The output voltage change per unit of time
while in hold. Commonly specified in V/s, V/ s or other convenient
units.
2001 Aug 03
Sample-and-hold amplifier
6
The basic circuit concept of the sample-and-hold circuit incorporates
diodes close the loop around the input amplifier to keep it from being
The switch control has a floating reference (Pin 7), referred to as the
logic reference which makes the sample-and-hold device compatible
Hold Mode Feedthrough — The percentage of an input sinusoidal
signal that is measured at the output of a sample-hold when it’s in
hold mode.
Hold Settling Time — The time required for the output to settle
within 1mV of final value after the “HOLD” logic command.
Hold Step — The voltage step at the output of the sample-and-hold
when switching from sample mode to hold mode with a steady (DC)
analog input voltage. Logic swing is 5 V.
Sample-to-Hold Offset Error — The difference in output voltage
between the time the switch starts to open, and the time when the
output has settled completely. It is caused by charge being
transferred to the hold capacitor switch as it opens.
Slew Rate — The fastest rate at which the sample-and-hold output
can change (specified in V/ s).
Threshold Level — That level which causes the switch control to
change state.
BASIC BLOCK DIAGRAM
the use of two (2) operational amplifiers and a switch control
mechanism (which determines sample, hold or track conditions).
The block diagram of the NE5537 is a closed loop, non-inverting
unity gain sample-and-hold system. The input buffer amplifier
supplies the current necessary to charge the hold capacitor, while
the output buffer amplifier closes the loop so that the output voltage
is identical to the input voltage (with consideration for input offset
voltage, offset current, and temperature variations which are
common to all sample-and-hold circuits, be they monolithic, hybrid
or modular).
When the sampling switch is open (in the hold mode), the clamping
overdriven into saturation.
The switch control is driven by external logic levels via a timing
sequence remote from the sample-and-hold device (See Figure 5).
to several types of external logic signals (TTL, PMOS, and CMOS).
The switching device operates at a threshold level of 1.4 V.
The switch mechanism is on (sampling an information stream) when
the logic level is high (Pin 8 is 1.4 V higher than Pin 7) and presents
a load of 5 A to the input logic signal. The analog sampled signal is
amplified, stored (in the external holding capacitor), and buffered. At
the end of the sampling period, the internal switch mechanism turns
SAMPLE
HOLD
ANALOG INPUT
Figure 5. Typical Connection
5V
0V
LOGIC
INPUT
3
8
V+
1
7
V–
4
6
5
C
h
SL00346
OUTPUT
NE5537
Product data