NE5537N NXP Semiconductors, NE5537N Datasheet - Page 3

• Manufacturer Part Number: NE5537N
• Manufacturer: NXP Semiconductors

Specifications of NE5537N

• Number Of Sample And Hold Elements: 1
• Power Supply Requirement: Dual
• Single Supply Voltage (typ): Not RequiredV
• Single Supply Voltage (min): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Package Type: PDIP
• Lead Free Status / RoHS Status: Compliant

1. Derate above 25 C at the following rates:
2. Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins may be equal to the supply
1. Unless otherwise specified, the following conditions apply: Unit is in “sample” mode. V
2. Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1 pF, for instance, will create an
3. Leakage current is measured at a junction temperature of 25 C. The effects of junction temperature rise due to power dissipation or
4. These parameters guaranteed over a supply voltage range of 5 V to 18 V.
Philips Semiconductors
ABSOLUTE MAXIMUM RATINGS
NOTES:
DC ELECTRICAL CHARACTERISTICS
NOTES:
2001 Aug 03
SYMBOL
V
P
V
T
T
T
V
V
I
I
I
SVRR
BIAS
BIAS
CC
SYMBOL
SYMBOL
amb
stg
sld
S
D
IN
OS
OS
Sample-and-hold amplifier
voltages without causing damage to the circuit. For proper logic operation, however, one of the logic pins must always be at least 2 V below
the positive supply and 3 V above the negative supply.
C
additional 0.5 mV step with a 5 V logic swing and a 0.01 F hold capacitor. Magnitude of the hold step is inversely proportional to hold
capacitor value.
elevated ambient can be calculated by doubling the 25 C value for each 11 C increase in chip temperature. Leakage is guaranteed over
full input signal range.
H
= 0.01 F, and R
N package at 9.3 mW/ C
D package at 8.3 mW/ C
Input offset voltage
In ut offset voltage
Input bias current
In ut bias current
Input impedance
Gain error
Feedthrough attenuation ratio at 1kHz
Output impedance
“HOLD” Step
Supply current
Logic and logic reference input current
Leakage current into hold capacitor
Acquisition time to 0.1%
Hold capacitor charging current
Supply voltage rejection ratio
Differential logic threshold
Voltage supply
Maximum power dissipation; T
Input voltage
Logic to logic reference differential voltage
Output short circuit duration
Hold capacitor short circuit duration
Operating ambient temperature range
Storage temperature range
Lead soldering temperature (10 sec max)
N package
D package
L
= 2 k . Logic reference voltage = 0 V and logic voltage = 2.5 V.
2
4
PARAMETER
PARAMETER
4
4
PARAMETER
amb
4
1
= 25 C (still-air)
2
T
–11.5 V
j
= 25 C; C
–10 V
1
T
3
T
T
Full temperature range
Full temperature range
Full temperature range
Full temperature range
j
j
j
TEST CONDITIONS
TEST CONDITIONS
= 25 C; “HOLD” mode
= 25 C, C
= 25 C “hold” mode
V
V
V
C
C
V
IN
IN
V
IN
H
H
T
T
T
T
T
T
OUT
H
T
–V
OUT
j
j
j
j
j
j
j
= 0.01 F; V
= 1000 pF
= 0.01 F
= 25 C
= 25 C
= 25 C
= 25 C
= 25 C
= 25 C
= 25 C
OUT
11.5 V; R
10 V; R
= 10 V;
= 0 V
H
= 2 V
= 0.01 F
S
L
= 15 V, T
L
= 2 k
OUT
= 10 k
3
Equal to supply voltage
= 0 V
j
–65 to +150
= 25 C, –11.5V
Indefinite
RATING
0 to +70
+7, –30
1160
1090
230
10
18
Min
0.8
80
80
Limits
0.004
10
Typ
110
0.5
1.0
4.5
1.4
10
90
20
2
2
6
4
5
V
10
IN
NE5537
11.5 V,
Max
0.01
0.02
100
100
2.5
7.5
2.4
10
50
10
7
4
6
Product data
UNIT
mW
mW
V
V
s
C
C
C
UNIT
UNIT
mV
mV
mV
mA
mA
nA
nA
dB
pA
dB
%
%
V
A
s
s