MT41J64M16LA-187E:B Micron Technology Inc, MT41J64M16LA-187E:B Datasheet - Page 153

• Manufacturer Part Number: MT41J64M16LA-187E:B
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J64M16LA-187E:B

• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Maximum Clock Rate: 1.066GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 265mA
• Pin Count: 96
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

READ Operation
Figure 68: READ Latency
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN
DQS, DQS#
Command
Address
CK#
DQ
CK
Bank a,
READ
Col n
T0
Notes:
CL = 8, AL = 0
READ bursts are initiated with a READ command. The starting column and bank ad-
dresses are provided with the READ command and auto precharge is either enabled or
disabled for that burst access. If auto precharge is enabled, the row being accessed is
automatically precharged at the completion of the burst. If auto precharge is disabled,
the row will be left open after the completion of the burst.
During READ bursts, the valid data-out element from the starting column address is
available READ latency (RL) clocks later. RL is defined as the sum of POSTED CAS ADDI-
TIVE latency (AL) and CAS latency (CL) (RL = AL + CL). The value of AL and CL is
programmable in the mode register via the MRS command. Each subsequent data-out
element will be valid nominally at the next positive or negative clock edge (that is, at the
next crossing of CK and CK#). Figure 68 shows an example of RL based on a CL setting
of 8 and an AL setting of 0.
DQS, DQS# is driven by the DRAM along with the output data. The initial low state on
DQS and HIGH state on DQS# is known as the READ preamble (
on DQS and the HIGH state on DQS#, coincident with the last data-out element, is
known as the READ postamble (
commands have been initiated, the DQ will go High-Z. A detailed explanation of
(valid data-out skew),
ted in Figure 79 (page 161). A detailed explanation of
CK) is also depicted in Figure 79 (page 161).
Data from any READ burst may be concatenated with data from a subsequent READ
command to provide a continuous flow of data. The first data element from the new
burst follows the last element of a completed burst. The new READ command should
be issued
(page 155). If BC4 is enabled,
output, as shown in Figure 70 (page 155). Nonconsecutive read data is reflected in Fig-
NOP
T7
1. DO n = data-out from column n.
2. Subsequent elements of data-out appear in the programmed order following DO n.
t
CCD cycles after the first READ command. This is shown for BL8 in Figure 69
NOP
T8
DO
n
t
QH (data-out window hold), and the valid data window are depic-
NOP
T9
153
t
CCD must still be met which will cause a gap in the data
t
RPST). Upon completion of a burst, assuming no other
NOP
T10
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Indicates A Break in
Time Scale
1Gb: x4, x8, x16 DDR3 SDRAM
NOP
T11
t
DQSCK (DQS transition skew to
Transitioning Data
© 2006 Micron Technology, Inc. All rights reserved.
T12
NOP
t
RPRE). The low state
READ Operation
NOP
T12
Don’t Care
t
DQSQ