MT48H4M16LFB4-75 IT:H Micron Technology Inc, MT48H4M16LFB4-75 IT:H Datasheet - Page 43

• Manufacturer Part Number: MT48H4M16LFB4-75 IT:H
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48H4M16LFB4-75 IT:H

• Organization: 4Mx16
• Density: 64Mb
• Address Bus: 14b
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 50mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Notes
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
10.
11. AC timing and I
12. Other input signals are allowed to transition no more than once every two clocks and
13. I
14. Timing actually specified by
15. Timing actually specified by
16. Timing actually specified by
17. Required clocks are specified by JEDEC functionality and are not dependent on any
18. The I
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on
22. V
1. All voltages referenced to V
2. This parameter is sampled. V
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH
7. AC characteristics assume
8. In addition to meeting the transition rate specification, the clock and CKE must tran-
9. Outputs measured for 1.8V at 0.9V with equivalent load:
Q
1.4V. f = 1 MHz.
with minimum cycle time and the outputs open.
operation over the full temperature range (0°C ≤ T
–40°C ≤ T
commands, before proper device operation is ensured. (V
ered up simultaneously. V
REFRESH command wake-ups should be repeated any time the
ment is exceeded.
sition between V
t
a reference to V
High-Z.
point. If the input transition time is longer than
enced at V
are otherwise at valid V
cycle rate.
minimum cycle rate.
timing parameter.
frequency alteration for the test condition.
cannot be greater than one-third of the cycle rate. V
a pulse width ≤3ns.
DD
HZ defines the time at which the output achieves the open circuit condition; it is not
DD
IH
is dependent on output loading and cycle rates. Specified values are obtained
specifications are tested after the device is properly initialized.
overshoot: V
DD
current will increase or decrease proportionally according to the amount of
A
t
CK = 7.5ns for -75 and
IL
≤ +85°C for industrial parts) is ensured.
20pF
(MAX) and V
OH
DD
IH
IH
or V
(MAX) = V
and V
tests have V
OL
IH
. The last valid data element will meet
IL
IH
SS
or V
t
43
SS
T = 1ns.
(or between V
(MIN) and no longer at the V
and V
t
t
t
.
DD
CKS; clock(s) specified as a reference only at minimum
WR plus
WR.
DD
IL
IL
/V
Q + 2V for a pulse width ≤3ns, and the pulse width
levels.
t
and V
CK = 8.0ns for -8.
SS
DD
Q must be at same potential.) The two AUTO
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Q = 1.7–1.95V; T
t
RP; clock(s) specified as a reference only at
IH
, with timing referenced to V
IL
64Mb: 4 Meg x 16 Mobile SDRAM
and V
t
T (MAX), then the timing is refer-
IH
A
) in a monotonic manner.
≤ +70°C for commercial parts;
IL
A
undershoot: V
= 25°C; pin under test biased at
IH
DD
/2 crossover point.
©2006 Micron Technology, Inc. All rights reserved.
and V
t
OH before going
t
REF refresh require-
DD
IL
IH
Q must be pow-
(MIN) = -2V for
/2 = crossover
Notes