NP8P128A13T1760E Micron Technology Inc, NP8P128A13T1760E Datasheet - Page 83
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NP8P128A13T1760E
Manufacturer Part Number
NP8P128A13T1760E
Description
Manufacturer
Micron Technology Inc
Datasheet
1.NP8P128A13T1760E.pdf
(94 pages)
Specifications of NP8P128A13T1760E
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NP8P128A13T1760E
Manufacturer:
TI
Quantity:
1 043
Company:
Part Number:
NP8P128A13T1760E
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Numonyx® Omneo™ P8P Datasheet
Figure 40: Write State Machine — Output Next State Table (Sheet 4)
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
August 2010
316144-07
"Illegal commands" include commands outside of the allowed command set (allowed commands: 40H [pgm], 20H [erase],
etc.)
If a "Read Array" is attempted while the device is busy writing or erasing, the result will be invalid data. The ID and Query
data are located at different locations in the address map.
1st and 2nd cycles of "2 cycles write commands" must be given to the same device address, or unexpected results will
occur.
The 2nd cycle of the following 2 cycle commands will be ignored by the user interface: Word Program Setup, Erase Setup,
OTP Setup, and Lock/Unlock/Lock-down/CR setup when issued in an "illegal condition". Illegal conditions are such as "pgm
setup while busy", "erase setup while busy", “Word program suspend”, etc. Thus for example the second cycle of an erase
command issued in program suspend will NOT resume the program operation.
The Clear Status command only clears the error bits in the Status Register if the device is not in the following modes: 1.
WSM running (Pgm Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, modes); 2. Suspend states (Pgm Suspend,
Pgm Suspend In Erase Suspend)
The "current state" is that of the "device"
Confirm commands (Lock Block, Unlock Block, Lock-Down Block) perform the operation and then move to the Ready
State.
Buffered programming will botch when a different block address (as compared to address given with E8 command) is
written during the BP Load1 and BP Load2 states
WA0 refers to the block address latched during the first write cycle of the current operation
Erase Setup,
OTP Setup,
BP: Setup, Load 1, Load 2, Confirm,
Word Pgm Setup,
SM Entry Setup, SM Exit Setup
Lock/CR Setup,
Lock/CR Setup in Erase Susp
OTP Busy
Ready, SM Ready
Erase Suspend,
BP Suspend
BP Busy,
Word Program Busy,
Erase Busy,
BP Busy
BP Busy in Erase Suspend
Word Pgm Suspend,
Word Pgm Busy in Erase Suspend,
Pgm Suspend In Erase Suspend
BP Suspend in Erase Suspend
SM Entry Busy
SM Exit Busy
Current chip state
Status Read
OTP Setup
(C0H)
(4)
Command Input to Chip and resulting Output Mux Next State
Status Read
Confirm (7)
Block
(01H)
Lock
Output mux does not change.
Confirm (7)
Lock-Down
Block
(2FH)
Status Read
Confirm (7)
RCR/ECR
(03H,04H)
Ready
Write
Array
Ready Array
Address
(FFFFH)
(WA0)
Block
Status Read
(all other codes)
Illegal Cmds (1)
Read Array
Completes
Operation
WSM
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