M393T2950CZ3-CCC Samsung Semiconductor, M393T2950CZ3-CCC Datasheet - Page 4

• Manufacturer Part Number: M393T2950CZ3-CCC
• Manufacturer: Samsung Semiconductor

Specifications of M393T2950CZ3-CCC

• Lead Free Status / RoHS Status: Compliant

3.0 Address Configuration
RDIMM
2.0 Features
1.0 DDR2 Registered DIMM Ordering Information
Note :
1. “Z” of Part number(11th digit) stand for Lead-free products.
2. “3” of Part number(12th digit) stand for Dummy Pad PCB products.
3. "A" of Part number(12th digit) stand for Parity Register products.
4. "92" of Part number(3~4th digit) stand for VLP(Very Low Profile) Register products.
M393T6553CZ3-CD5/CC
M393T6553CZA-CF7/E6/D5/CC
M393T2953CZ3-CD5/CC
M393T2953CZA-CF7/E6/D5/CC
M393T2950CZ3-CD5/CC
M393T2950CZA-CF7/E6/D5/CC
M393T5750CZ3-CD5/CC
M393T5750CZA-CF7/E6/D5/CC
Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
• Performance range
• JEDEC standard 1.8V ± 0.1V Power Supply
• V
• 200 MHz f
• 4 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5, 6
• Programmable Additive Latency: 0, 1 , 2 , 3 ,4 and 5
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination with selectable values(50/75/150 ohms or disable)
• PASR(Partial Array Self Refresh)
• Average Refresh Period 7.8us at lower than T
• Serial presence detect with EEPROM
• DDR2 SDRAM Package: 60ball FBGA - 128Mx4/64Mx8
• All of Lead-free products are compliant for RoHS
- support High Temperature Self-Refresh rate enable feature
DDQ
128Mx4(512Mb) based Module
64Mx8(512Mb) based Module
CL-tRCD-tRP
Speed@CL3
Speed@CL4
Speed@CL5
Speed@CL6
Part Number
= 1.8V ± 0.1V
CK
Organization
for 400Mb/sec/pin, 267MHz f
F7(DDR2-800)
Density
512MB
512MB
1GB
1GB
1GB
1GB
2GB
2GB
6-6-6
400
533
800
-
CK
Organization
Row Address
CASE
for 533Mb/sec/pin, 333MHz f
128Mx72
128Mx72
128Mx72
128Mx72
256Mx72
256Mx72
64Mx72
64Mx72
A0-A13
A0-A13
85°C, 3.9us at 85°C < T
E6(DDR2-667)
128Mx4(K4T51043QC)*18EA
128Mx4(K4T51043QC)*18EA
128Mx4(K4T51043QC)*36EA
128Mx4(K4T51043QC)*36EA
64Mx8(K4T51083QC)*18EA
64Mx8(K4T51083QC)*18EA
64Mx8(K4T51083QC)*9EA
64Mx8(K4T51083QC)*9EA
5-5-5
Component Composition
400
533
667
-
4 of 25
Column Address
A0-A9,A11
CASE
CK
A0-A9
for 667Mb/sec/pin, 400MHz f
< 95 °C
D5(DDR2-533)
4-4-4
400
533
533
-
Number of Rank
Bank Address
BA0-BA1
BA0-BA1
1
1
2
2
1
1
2
2
CK
for 800Mb/sec/pin
CC(DDR2-400)
Parity Register
3-3-3
DDR2 SDRAM
400
400
Rev. 1.8 May 2007
-
-
O
O
O
O
X
X
X
X
Auto Precharge
A10
A10
30.00mm
30.00mm
30.00mm
30.00mm
30.00mm
30.00mm
30.00mm
30.00mm
Height
Mbps
Mbps
Mbps
Mbps
Unit
CK