MT18HTF25672PDY-80EE1 Micron Technology Inc, MT18HTF25672PDY-80EE1 Datasheet
MT18HTF25672PDY-80EE1
Specifications of MT18HTF25672PDY-80EE1
Related parts for MT18HTF25672PDY-80EE1
MT18HTF25672PDY-80EE1 Summary of contents
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... DIMM (MO-237 R/C “B” will add one clock cycle to CL. 2. Not available in 512MB module density RCD (ns) (ns) – 12.5 12.5 – 400 15 15 400 15 15 ...
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... Part Numbers and Timing Parameters – 512MB Modules Base device: MT47H32M8, 256Mb DDR2 SDRAM 1 Part Number MT18HTF6472(P)D(P)Y-667__ MT18HTF6472(P)D(P)Y-53E__ MT18HTF6472(P)D(P)Y-40E__ Table 4: Part Numbers and Timing Parameters – 1GB Modules Base device: MT47H64M8, 512Mb DDR2 SDRAM 1 Part Number MT18HTF12872(P)D(P)Y-80E__ MT18HTF12872(P)D(P)Y-800__ MT18HTF12872(P)D(P)Y-667__ MT18HTF12872(P)D(P)Y-53E__ MT18HTF12872(P)D(P)Y-40E__ Table 5: Part Numbers and Timing Parameters – ...
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Pin Assignments and Descriptions Table 6: Pin Assignments 240-Pin RDIMM Front Pin Symbol Pin Symbol Pin Symbol Pin Symbol DQ19 61 REF DQ0 33 DQ24 63 4 DQ1 34 ...
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... I/O (SSTL18) Data input/output: Bidirectional data bus. CB0–CB7 I/O (SSTL18) Check bits. SDA I/O Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module Output Parity error found on the address and control bus. RR ...
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Functional Block Diagram Figure 2: Functional Block Diagram RS1# RS0# DQS0 DQS0# DM0/DQS9 NC/DQS9# DM/ RDQS DQ DQ0 DQ DQ1 DQ DQ2 DQ DQ3 DQ4 DQ DQ DQ5 DQ DQ6 DQ DQ7 DQS1 DQS1# DM1/DQS10 NC/DQS10# DM/ RDQS DQ DQ8 ...
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... DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer ...
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... When inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and real- istic than a gross estimation of module capacitance. Simulations can then render a considerably more accurate result. JEDEC modules are now designed by using simula- tions to close timing budgets ...
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... HIGH between valid commands; Address bus inputs are stable during DESELECTs; Data bus inputs are switching Notes Value calculated as one module rank in this operating condition; all other module ranks Value calculated reflects all module ranks in this operating condition. PDF: 09005aef80e935cd/Source: 09005aef80e934a6 HTF18C64_128_256x72D ...
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... S# is HIGH between valid commands; Address bus inputs are stable during DESELECTs; Data bus inputs are switching Notes Value calculated as one module rank in this operating condition; all other module ranks Value calculated reflects all module ranks in this operating condition. PDF: 09005aef80e935cd/Source: 09005aef80e934a6 HTF18C64_128_256x72D ...
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... S# is HIGH between valid commands; Address bus inputs are stable during DESELECTs; Data bus inputs are switching Notes Value calculated as one module rank in this operating condition; all other module ranks Value calculated reflects all module ranks in this operating condition. PDF: 09005aef80e935cd/Source: 09005aef80e934a6 HTF18C64_128_256x72D ...
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... AC Timing and Operating Conditions Recommended AC operating conditions are given in the DDR2 component data sheets. Component specifications are available on Micron’s Web site. Module speed grades correlate with component speed grades as shown in the following table: Table 12: Module and Component Speed Grade Table PDF: 09005aef80e935cd/Source: 09005aef80e934a6 HTF18C64_128_256x72D ...
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... Timing and switching specifications for the register listed above are critical for proper oper- ation of the DDR2 SDRAM registered DIMMs. These are meant subset of the param- eters for the specific device used on the module. Detailed information for this register is available in JEDEC Standard JESD82. ...
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PLL Table 14: PLL (CU877 device or equivalent JESD82-8.01) Parameter Symbol V DC high-level input voltage DC low-level input voltage V Input voltage (limits high-level input voltage low-level input voltage Input differential-pair cross V voltage ...
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Table 15: PLL Clock Driver Timing Requirements and Switching Characteristics Parameter Stabilization time Input clock slew rate SSC modulation frequency SSC clock input frequency deviation PLL loop bandwidth (-3dB from unity gain) Notes: 1. PLL timing and switching specifications are ...
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Serial Presence-Detect Table 16: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage 3mA OUT Input ...
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... Number of SPD bytes used by Micron 1 Total number of bytes in SPD device 2 Fundamental memory type 3 Number of row addresses on SDRAM 4 Number of column addresses on SDRAM 5 DIMM height and module ranks 6 Module data width 7 Reserved 8 Module voltage interface levels t 9 SDRAM cycle time, CK (CL = MAX value, see byte ...
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... AC, MAX MIN row precharge time MIN row active to row t active, RRD 29 MIN RAS# to CAS# delay, t RCD t 30 MIN RAS# pulse width, RAS 31 Module rank density 32 Address and command setup t time Address and command hold t time Data/data mask input setup t time Data/data mask input hold ...
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... SPD revision 63 Checksum for bytes 0–62 ECC/ECC and parity 64 Manufacturer’s JEDEC ID code 65-71 Manufacturer’s JEDEC ID code 72 Manufacturing location 73-90 Module part number (ASCII) 91 PCB identification code 92 Identification code (continued) 93 Year of manufacture in BCD 94 Week of manufacture in BCD 95– Module serial number 98 99– ...
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... TYP. 4.840 (123.0) TYP. BACK VIEW U17 U16 U18 U19 5.0 (0.197) TYP. 55.0 (2.165) TYP. ® their respective owners. 19 Module Dimensions U10 U11 U12 30.50 (1.20) 29.85 (1.175) 17.78 (0.700) TYP. 10.00 (0.394) TYP. PIN 120 U20 U21 U22 PIN 121 Micron Technology, Inc., reserves the right to change products or specifications without notice. © ...