ISP1760BEGA STEricsson, ISP1760BEGA Datasheet - Page 45

• Manufacturer Part Number: ISP1760BEGA
• Manufacturer: STEricsson

Specifications of ISP1760BEGA

• Package Type: LQFP
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Table 44.
Table 45.
[1]
CD00222702
Product data sheet
Bit
31 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
ATL Done Timeout register (address 0338h) bit description
Memory register (address 033Ch) bit allocation
Symbol
ATL_DONE_
TIMEOUT[31:0]
8.3.7 ATL Done Timeout register
8.3.8 Memory register
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
Table 43.
The bit description of the ATL Done Timeout register is given in
The Memory register contains the base memory read address and the respective bank.
This register needs to be set only before a first memory read cycle. Once written, the
address will be latched for the bank and will be incremented for every read of that bank,
until a new address for that bank is written to change the address pointer.
The bit description of the register is given in
Bit
0
Access
R/W
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
Symbol
ATL_BUF_
FILL
Buffer Status register (address 0334h) bit description
Value
0000 0000h
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Description
ATL Buffer Filled:
1 — Indicates one of the ATL PTDs is filled, and the ATL PTD area will be
processed.
0 — Indicates there is no PTD in this area. Therefore, processing of the ATL
PTDs will completely be skipped.
reserved
Rev. 08 — 13 April 2010
START_ADDR_MEM_READ[15:8]
START_ADDR_MEM_READ[7:0]
Description
ATL Done Timeout: This register determines the ATL done
time-out interrupt. This register defines the time-out in
milliseconds after which the ISP1760 asserts the INT line, if
enabled. It is applicable to ATL done PTDs only.
[1]
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
reserved
[1]
R/W
R/W
R/W
R/W
Table
27
19
11
0
0
0
3
0
Embedded Hi-Speed USB host controller
45.
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
…continued
Table
MEM_BANK_SEL[1:0]
© ST-ERICSSON 2010. All rights reserved.
R/W
R/W
R/W
R/W
25
17
44.
0
0
9
0
1
0
ISP1760
R/W
R/W
R/W
R/W
45 of 105
24
16
0
0
8
0
0
0