ISP1760BEGA STEricsson, ISP1760BEGA Datasheet - Page 53

• Manufacturer Part Number: ISP1760BEGA
• Manufacturer: STEricsson

Specifications of ISP1760BEGA

• Package Type: LQFP
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

CD00222702
Product data sheet
Table 60.
Bit
31 to 10 -
9
8
7
6
5
4
3
Symbol
ISO_IRQ
ATL_IRQ
INT_IRQ
CLK
READY
HC_
SUSP
-
DMAEOT
INT
Interrupt register (address 0310h) bit description
Description
reserved; write reset value
ISO IRQ: Indicates that an ISO PTD was completed, or the PTDs
corresponding to the bits set in the ISO IRQ Mask AND or ISO IRQ Mask
OR register bits combination were completed. The IRQ line will be asserted
if the respective enable bit in the HCInterruptEnable register is set.
0 — No ISO PTD event occurred.
1 — ISO PTD event occurred.
For details, see
ATL IRQ: Indicates that an ATL PTD was completed, or the PTDs
corresponding to the bits set in the ATL IRQ Mask AND or ATL IRQ Mask
OR register bits combination were completed. The IRQ line will be asserted
if the respective enable bit in the HCInterruptEnable register is set.
0 — No ATL PTD event occurred.
1 — ATL PTD event occurred.
For details, see
INT IRQ: Indicates that an INT PTD was completed, or the PTDs
corresponding to the bits set in the INT IRQ Mask AND or INT IRQ Mask OR
register bits combination were completed. The IRQ line will be asserted if the
respective enable bit in the HCInterruptEnable register is set.
0 — No INT PTD event occurred.
1 — INT PTD event occurred.
For details, see
Clock Ready: Indicates that internal clock signals are running stable. The
IRQ line will be asserted if the respective enable bit in the
HCInterruptEnable register is set.
0 — No CLKREADY event has occurred.
1 — CLKREADY event occurred.
Host Controller Suspend: Indicates that the host controller has entered
suspend mode. The IRQ line will be asserted if the respective enable bit in
the HCInterruptEnable register is set.
0 — The host controller did not enter suspend mode.
1 — The host controller entered suspend mode.
If the ISR accesses the ISP1760, it will wake up for the time specified in bits
31 to 16 of the Power Down Control register.
reserved; write reset value
DMA EOT Interrupt: Indicates the DMA transfer completion. The IRQ line
will be asserted if the respective enable bit in the HCInterruptEnable register
is set.
0 — No DMA transfer is completed.
1 — DMA transfer is complete.
Rev. 08 — 13 April 2010
Section
Section
Section
7.4.
7.4.
7.4.
Embedded Hi-Speed USB host controller
© ST-ERICSSON 2010. All rights reserved.
ISP1760
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