NH82801HBM S LA5Q Intel, NH82801HBM S LA5Q Datasheet - Page 13

• Manufacturer Part Number: NH82801HBM S LA5Q
• Manufacturer: Intel

Specifications of NH82801HBM S LA5Q

• Lead Free Status / RoHS Status: Compliant

Errata
1.
Problem:
Implication: When in Legacy TCO mode, all ICH8 TCO SMBus slave unit functionality is assigned to
Workaround:All Desktop platforms
Status:
2.
Problem:
Implication: None known.
Workaround:None.
Status:
Intel
• Connect SMBus and SMLINK pins together (connect SMLINK0 to SMBCLK and SMLINK1 to
®
SMBDATA) and program STRP0.TCOMODE (FISBA+000h:bit 7) to ‘0b’ in the flash descriptor
region in the SPI part.
— If no descriptor region is in SPI or SPI is not used, connect the SMBus and SMLINK pins
ICH8 Family Specification Update
together as described above.
Intel
The ICH8 B0 stepping implements the TCO Mode soft strap in the VccCL power well.
When VccCL power is lost or a global reset is asserted, the TCO Slave Unit Mode will be
set to Legacy TCO mode.
the SMLINK[1:0] interface, not the SMBus interface. SMBus masters connected to the
SMBus will not be able to access the ICH8 TCO slave unit.
No fix (Desktop Only). For affected steppings, see the Summary Table of Changes.
Intel
The ICH8 1.5 Gb/s SATA transmit buffers have been designed to maximize performance
and robustness over a variety of routing scenarios. As a result, the ICH8 SATA 1.5 Gb/s
(Gen1i) transmit signaling voltage levels may exceed the maximum motherboard TX
connector and device RX connector voltage specifications (section 7.2.1 of Serial ATA
Specification, rev 2.5).
No plan to fix. For affected steppings, see the Summary Table of Changes.
®
®
ICH8 TCO Mode Strap
ICH8 1.5 Gb/s SATA Signal Voltage Level
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