NH82801HBM S LA5Q Intel, NH82801HBM S LA5Q Datasheet - Page 27

• Manufacturer Part Number: NH82801HBM S LA5Q
• Manufacturer: Intel

Specifications of NH82801HBM S LA5Q

• Lead Free Status / RoHS Status: Compliant

Intel
®
ICH8 Family Specification Update
15:12
7:2
Bit
26
25
24
23
22
21
20
19
18
17
16
11
10
9
8
1
0
Exchanged (X): When set to one this bit indicates that a change in device presence
has been detected since the last time this bit was cleared. This bit shall always be set to
1 anytime a COMINIT signal is received. This bit is reflected in the P0IS.PCS bit.
Unrecognized FIS Type (F): Indicates that one or more FISs were received by the
Transport layer with good CRC, but had a type field that was not recognized.
Transport state transition error (T): Indicates that an error has occurred in the
transition
from one state to another within the Transport layer since the last time this bit was
cleared.
Transport state transition error (T): Indicates that an error has occurred in the
transition
from one state to another within the Transport layer since the last time this bit was
cleared.
Handshake (H): Indicates that one or more R_ERR handshake response was received
in response to frame transmission. Such errors may be the result of a CRC error
detected by the recipient, a disparity or 8b/10b decoding error, or other error condition
leading to a negative handshake on a transmitted frame.
CRC Error (C): Indicates that one or more CRC errors occurred with the Link Layer.
Disparity Error (D): This field is not used by AHCI.
10b to 8b Decode Error (B): Indicates that one or more 10b to 8b decoding errors
occurred.
Comm Wake (W): Indicates that a Comm Wake signal was detected by the Phy.
Phy Internal Error (I): Indicates that the Phy detected some internal error.
PhyRdy Change (N): When set to 1 this bit indicates that the internal PhyRdy signal
changed state since the last time this bit was cleared. In the ICH8, this bit will be set
when PhyRdy changes from a 0 -> 1 or a 1 -> 0. The state of this bit is then reflected
in the PxIS.PRCS interrupt status bit and an interrupt will be generated if enabled.
Software clears this bit by writing a 1 to it.
Reserved
Internal Error (E): The SATA controller failed due to a master or target abort when
attempting to access system memory.
Protocol Error (P): A violation of the Serial ATA protocol was detected.
Note: The ICH8 does not set this bit for all protocol violations that may occur on the
SATA link.
Persistent Communication or Data Integrity Error (C): A communication error
that was not recovered occurred that is expected to be persistent. Persistent
communications errors may arise from faulty interconnect with the device, from a
device that has been removed or has failed, or a number of other causes.
Transient Data Integrity Error (T): A data integrity error occurred that was not
recovered by the interface.
Reserved.
Recovered Communications Error (M): Communications between the device and
host was temporarily lost but was re-established. This can arise from a device
temporarily being removed, from a temporary loss of Phy synchronization, or from
other causes and may be derived from the PhyNRdy signal between the Phy and Link
layers.
Recovered Data Integrity Error (I): A data integrity error occurred that was
recovered by the interface through a retry operation or other recovery action.
Description
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