NH82801HBM S LA5Q Intel, NH82801HBM S LA5Q Datasheet - Page 28

• Manufacturer Part Number: NH82801HBM S LA5Q
• Manufacturer: Intel

Specifications of NH82801HBM S LA5Q

• Lead Free Status / RoHS Status: Compliant

6.
The following change applies to Section 12.4.2.7 of the Datasheet.
7.
The following change applies to Section 5.17.1 of the Datasheet.
The main counter is clocked by the 14.31818 MHz clock, synchronized into the
8.
In Figure 43 of the Datasheet, t216 is removed from the timing figure.
9.
The following change applies to Section 9.10.4 of the Datasheet.
10.
The following is added to Table 147: Ballout by Signal Name (Mobile Only) of the Datasheet
Intel
VSS
Ball Name
®
ICH8 Family Specification Update
SATA Interlock Switch State (ISS) Bit Clarification
HPET Timer
Timing Figure Clarification
GPIO_USE_SEL Override Register Description Correction
Add Ballout AH19(VSS) to Table 147
31:0
AH19
Bit
13
Ball#
GPIO_USE_SEL Override [31:0] — R/W.
GPIO signals (if it exists).
0 = GPIO_USE_SEL register determines the pin usage of native function or GPIO.
1 = Signal is used as native function regardeless of setting in GPIO_USE_SEL register.
Once a bit is set to 1b, it can only be cleared by a reset. Bits 31:24 and 15:8 are cleared by
RSMRST# and CF9h events. Bits 23:16 and 7:0 are cleared by PLTRST# events.
If the corresponding GPIO is not muxed with Native functionality or not implemented at all, this bit
has no effect.
This register corresponds to GPIO[31:0].
Interlock Switch State (ISS)— RO. For systems that support interlock switches
(via CAP.SIS [ABAR+00h:bit28]), if an interlock switch exists on this port (via ISP in
this register), this bit indicates the current state of the interlock switch. A 0 indicates
the switch is closed, and a 1 indicates the switch is opened.
For systems that do not support interlock switches (CAP.SIS=0), this bit reports 0.
Description
Each bit in this register corresponds to one of the
125 MHz
domain.
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