FDC37M707-MS Standard Microsystems (SMSC), FDC37M707-MS Datasheet - Page 127

• Manufacturer Part Number: FDC37M707-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37M707-MS

• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

The FDC37M70x implements a group nSMI
output pin. The System Management Interrupt
is a non-maskable interrupt with the highest
priority
management. The nSMI group interrupt output
consists of the enabled interrupts from each of
the functional blocks in the chip. The interrupts
are enabled onto the group nSMI output via the
SMI Enable Registers 1 and 2. The nSMI output
is then enabled onto the group nSMI output
frame in the Serial IRQ stream via bit[6] in the
SMI Enable Register 2.
The logic equation for the nSMI output is as
follows:
nSMI
REGISTERS
The following registers can be accessed when in
configuration
Registers B4-B7 and when not in configuration
they can be accessed through the Index and
Data Register (refer to Table 49B).
SMI Enable Registers
SMI Enable Register 1
(Configuration Register B4, Logical Device 8)
This register is used to enable the different
interrupt sources onto the group nSMI output.
SMI Enable Register 2
(Configuration Register B5, Logical Device 8)
This register is used to enable additional
interrupt sources onto the group nSMI output.
This register is also used to enable the group
nSMI output onto the nSMI Serial IRQ frame
and the routing of 8042 P12 internally to nSMI.
=
(EN_U2INT
(EN_U1INT
(EN_FINT
(EN_WDT
(EN_MINT
(EN_KINT
(EN_IRINT and IRQ_IRINT)
level
(EN_PINT
mode
used
and
and
and
and
at
for
and
and
and
Logical
transparent
IRQ_U2INT)
IRQ_U1INT)
IRQ_WDT)
IRQ_MINT)
IRQ_FINT)
IRQ_KINT)
IRQ_PINT)
Device
power
or
or
or
or
or
or
or
8,
127
SMI Status Registers
SMI Status Register 1
(Configuration Register B6, Logical Device 8)
This register is used to read the status of the
SMI input events. Note: The status bit gets set
whether or not the interrupt is enabled onto the
group SMI output.
SMI Status Register 2
(Configuration Register B7, Logical Device 8)
PME SUPPORT
The FDC37M70x offers support for power
management events (PMEs) also known as
ACPI SCI events. A power management event
is requested by an ACPI function via the
assertion
FDC37M70x, only active transitions on the ring
indicator inputs nRI1 and nRI2, active keyboard-
clock edges (high to low) and active mouse-
clock edges (high to low) can assert the nPME
signal.
output.
nPME
configuration registers in logical device number
eight.
LD8:CRC5.0, globally controls PME Wake-up
events. When PME_En is inactive, the nPME
signal can not be asserted. When PME_En is
asserted, any wake source whose individual
PME Wake Enable register bit, LD8:CRC8, is
asserted can cause nPME to become asserted.
The PME Wake Status register, LD8:CRC7,
indicates which wake source has asserted the
nPME signal. The PME Status bit, PME_Status,
LD8:CR6.0, is asserted by active transitions of
PME Wake sources. PME_Status will become
asserted independent of the state of the global
PME
CONFIGURATION section for further details.
enable,
functionality
nPME is an active low open-drain
The
of
the
PME
PME_En.
nPME
is
Enable
controlled
signal.
Refer
bit,
PME_En,
by
to
In
the
the
the