ISP1760ETUM STEricsson, ISP1760ETUM Datasheet - Page 36

• Manufacturer Part Number: ISP1760ETUM
• Manufacturer: STEricsson

Specifications of ISP1760ETUM

• Package Type: TFBGA
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Table 23.
[1]
CD00222702
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
PORTSC1 - Port Status and Control 1 register (address 0064h) bit allocation
8.2.6 PORTSC1 register
SUSP
R/W
R/W
R/W
31
23
15
R
0
0
0
7
0
PIC[1:0]
Table 22.
[1]
The Port Status and Control (PORTSC) register (bit allocation:
well. It is reset by hardware only when the auxiliary power is initially applied or in response
to a host controller reset. The initial conditions of a port are:
If the port has power control, software cannot change the state of the port until it sets port
power bits. Software must not attempt to change the state of the port until the power is
stable on the port (maximum delay is 20 ms from the transition).
Bit
31 to 1
0
•
•
For details on register bit description, refer to
Universal Serial Bus Rev.
No peripheral connected
Port disabled
R/W
R/W
FPR
R/W
30
22
14
R
0
0
0
6
0
reserved
Symbol
-
CF
CONFIGFLAG - Configure Flag register (address 0060h) bit description
[1]
R/W
R/W
R/W
R/W
PO
29
21
13
0
0
1
5
0
Description
reserved
Configure Flag: The host software sets this bit as the last action when it is
configuring the host controller. This bit controls the default port-routing
control logic.
Rev. 08 — 13 April 2010
1.0”.
reserved
R/W
R/W
R/W
R/W
PP
28
20
12
0
0
0
4
0
[1]
reserved
[1]
Ref. 2 “Enhanced Host Controller Interface Specification for
[1]
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
Embedded Hi-Speed USB host controller
LS[1:0]
PED
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
PTC[3:0]
Table
reserved
ECSC
© ST-ERICSSON 2010. All rights reserved.
R/W
R/W
R/W
R/W
23) is in the power
25
17
0
0
9
0
1
0
ISP1760
[1]
ECCS
R/W
R/W
PR
36 of 105
24
16
R
R
0
0
8
0
0
0