ISP1760ETUM STEricsson, ISP1760ETUM Datasheet - Page 43

• Manufacturer Part Number: ISP1760ETUM
• Manufacturer: STEricsson

Specifications of ISP1760ETUM

• Package Type: TFBGA
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Table 40.
[1]
CD00222702
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
DMA Configuration register (address 0330h) bit allocation
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
Table 41.
Bit
31 to 8
7 to 4
3 to 2
1
0
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
Symbol
DMA_COUNTER[23:0] DMA Counter: The number of bytes to be transferred (read or
-
BURST_LEN[1:0]
ENABLE_DMA
DMA_READ_WRITE_
SEL
reserved
DMA Configuration register (address 0330h) bit description
[1]
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 08 — 13 April 2010
DMA_COUNTER[23:16]
DMA_COUNTER[15:8]
DMA_COUNTER[7:0]
R/W
R/W
R/W
R/W
28
20
12
Description
write).
Remark: Different number of bursts will be generated for the
same transfer length programmed in 16-bit and 32-bit modes
because DMA_COUNTER is in number of bytes.
reserved
DMA Burst Length:
00 — Single DMA burst
01 — 4-cycle DMA burst
10 — 8-cycle DMA burst
11 — 16-cycle DMA burst
Enable DMA:
0 — Terminate DMA
1 — Enable DMA
DMA Read/Write Select: Indicates if the DMA operation is a
write or read to or from the ISP1760.
0 — DMA write to the ISP1760 internal RAM is set
1 — DMA read from the ISP1760 internal RAM
0
0
0
4
0
R/W
R/W
R/W
R/W
BURST_LEN[1:0]
27
19
11
0
0
0
3
0
Embedded Hi-Speed USB host controller
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
ENABLE_
DMA
© ST-ERICSSON 2010. All rights reserved.
R/W
R/W
R/W
R/W
17
25
1
0
0
0
9
0
ISP1760
DMA_READ
_WRITE_
R/W
R/W
R/W
SEL
R/W
24
16
43 of 105
0
0
0
8
0
0