ISP1760ETUM STEricsson, ISP1760ETUM Datasheet - Page 41

• Manufacturer Part Number: ISP1760ETUM
• Manufacturer: STEricsson

Specifications of ISP1760ETUM

• Package Type: TFBGA
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Table 36.
CD00222702
Product data sheet
Bit
31 to 0 CHIPID[31:0] R
Symbol
Chip ID - Chip Identifier register (address 0304h) bit description
8.3.2 Chip ID register
Access Value
Table 35.
Read this register to get the ID of the ISP1760. The upper word of the register contains
the hardware version number and the lower word contains the chip ID.
bit description of the register.
Bit
31
30 to 16
15
14 to 9
8
7
6
5
4 to 3
2
1
0
0001 1761h Chip ID: This register represents the hardware version number (0001h) and
Symbol
ALL_ATX_RESET
-
ANA_DIGI_OC
-
DATA_BUS_WIDTH Data Bus Width:
-
DACK_POL
DREQ_POL
-
INTR_POL
INTR_LEVEL
GLOBAL_INTR_EN
HW Mode Control - Hardware Mode Control register (address 0300h) bit
description
Description
the chip ID (1761h).
Remark: The chip ID is for internal use to identify the ISP176x product
family.
Rev. 08 — 13 April 2010
Description
All ATX Reset: For debugging purposes (not used normally).
1 — Enable reset, then write back logic 0
0 — No reset
reserved; write logic 0
Analog Digital Overcurrent: This bit selects analog or digital
overcurrent detection on pins OC1_N, OC2_N and OC3_N.
0 — Digital overcurrent
1 — Analog overcurrent
reserved; write logic 0
0 — Defines a 16-bit data bus width
1 — Sets a 32-bit data bus width
reserved; write logic 0
DACK Polarity:
1 — Indicates that the DACK input is active HIGH
0 — Indicates active LOW
DREQ Polarity:
1 — Indicates that the DREQ output is active HIGH
0 — Indicates active LOW
reserved; write logic 0
Interrupt Polarity:
0 — Active LOW
1 — Active HIGH
Interrupt Level:
0 — INT is level triggered.
1 — INT is edge triggered. A pulse of certain width is generated.
Global Interrupt Enable: This bit must be set to logic 1 to
enable the IRQ signal assertion.
0 — IRQ assertion is disabled. IRQ will never be asserted,
regardless of other settings or IRQ events.
1 — IRQ assertion is enabled. IRQ will be asserted according to
the Interrupt Enable register, and events setting and occurrence.
Embedded Hi-Speed USB host controller
© ST-ERICSSON 2010. All rights reserved.
Table 36
ISP1760
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