UPD720122GC-9EU-A Renesas Electronics America, UPD720122GC-9EU-A Datasheet
UPD720122GC-9EU-A
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UPD720122GC-9EU-A Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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The PD720122 is USB2.0 Generic Device Controller, which combines the NEC Electronics USB2.0 PHY and End-point Controller. The Controller has certified by USB Implementers Forum. End-point Controller has banked two Bulk End-point and one Interrupt End-point, and selectable three ...
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BLOCK DIAGRAM EPC2 Core Protocol Controller BIU Core CPU BUS EP0 Control IN 64 Byte EP0 Control OUT 64 Byte Local BUS EP3 Interrupt IN 8 Byte PHY Core : USB2.0 transceiver with serial interface engine EPC2 Core : Endpoint ...
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PIN CONFIGURATION • 100-pin plastic TQFP (Fine pitch) (14 × 14) µ PD720122GC-9EU µ PD720122GC-9EU RESETB 2 GND 3 XIN_CLK 4 XOUT 5 GND 6 CSB 7 INTB_ALL/ALE/ALE 8 A1/INTB_ALL/INTB_ALL 9 A2/Reserved/Reserved 10 A3/Reserved/Reserved 11 A4/Reserved/Reserved 12 ...
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PD720122GC-9EU, 720122GC-9EU-A Pin Pin Name Pin Name No. Function1 Function2 RESETB RESETB 3 GND GND 4 XIN_CLK XIN_CLK 5 XOUT XOUT 6 GND GND 7 CSB CSB 8 INTB_ALL ALE 9 A1 INTB_ALL ...
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PD720122GC-9EU, 720122GC-9EU-A Pin Pin Name Pin Name No. Fucntion1 Function2 FM21 FM21 53 EP2_DRQB EP2_DRQB 54 EP2_DACKB EP2_DACKB 55 EP2_WRB EP2_WRB 56 EP2_TCB EP2_TCB 57 LD0 LD0 58 LD1 LD1 59 LD2 LD2 ...
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FBGA (11 × 11) µ PD720122F1-DN2 µ PD720122F1-DN2 BUNRI AV ( LD15 NC RREF LD13 LD14 GND RPU 20 ...
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PD720122F1-DN2, 720122F1-DN2-A Pin Pin Name Pin Name No. Function1 Function2 Reserved 3 D10 Reserved 4 D12 Reserved 5 D15 Reserved 6 GND GND 7 INT1B INT1B 8 ACTIVE ACTIVE EP1_DACKB ...
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PD720122F1-DN2, 720122F1-DN2-A Pin Pin Name Pin Name No. Function1 Function2 51 SCAN0 SCAN0 52 EP1_DRQB EP1_DRQB 53 EP1_RDB EP1_RDB EP2_DRQB EP2_DRQB 56 EP2_WRB EP2_WRB 57 LD1 LD1 58 LD5 LD5 59 LD8 LD8 60 LD10 ...
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PIN INFORMATION Pin Name I/O Buffer Type RESETB tolerant Input Schmitt XIN_CLK I 3.3 V Input XOUT O 3.3 V Output CSB tolerant Input INTB_ALL tolerant Output ALE I 5 ...
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Pin Name I/O Buffer Type RSDM O USB full speed D- O M(1: tolerant Input VBUS tolerant Input GND SS ...
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ELECTRICAL SPECIFICATIONS 2.1 Buffer List • 3.3 V oscillator interface XIN,XOUT • 3.3 V input buffer FM21,SCAN(1:0) • 5V torelant input buffer RESETB,CSB,A(7:0),WRB,RDB,ACTIVE,EP1_DACKB,EP1_RDB,EP1_TCB,EP2_DACKB,EP2_WRB, EP2_TCB,BUNRI,M0,M1,VBUS,ALE • 5V torelant output buffer INTB_ALL,INT0B,INT1B,INT2B,M2,EP1_DRQB,EP2_DRQB • 5V torelant I/O buffer D(15:0),LD(15:0),AD(7:0),D0,AD(7:1),D(15:8) • USB interface ...
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Terms Used in Recommended Operating Range Parameter Symbol Power supply voltage V DD High-level input voltage V IH Low-level input voltage V IL Hysteresys voltage V H Input rise time t ri Input fall time t fi Terms Used in ...
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Absolute Maximum Ratings Parameter Symbol Voltage I/O voltage V Note 1 Note 2 Output current Note 3 Operating ambient temperature Storage temperature Notes torelant input buffer, output buffer, I/O buffer 2. 3.3 V input buffer,3.3 V ...
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DC Characteristics The DC characteristics are classified into those of the USB interface and those of the BIU block. 2.5.1 DC characteristics of USB interface Parameter Serial resistor between DP (DM) and RSDP (RSDM) Driver output resistance (also serves ...
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Figure 2-1. Differential Input Sensitivity Range for Low-/Full-Speed Differential input voltage range −1.0 0.0 0.2 0.4 0.6 0.8 1.0 Input voltage range (volts) Figure 2-2. Full-Speed Buffer Voh/Ioh Characteristics for High-Speed Capable Transceiver V –3.3 V –2.8 V –2.3 DD ...
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Figure 2-3. Full-Speed Buffer Vol/Iol Characteristics for High-Speed Capable Transceiver 0.5 Figure 2-4. Receiver Sensitivity for Transceiver at D+/D− Level 1 Level 1.5 2 Vout (V) Point 3 Point 4 ...
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Figure 2-5. Receiver Measurement Fixtures Test supply voltage 15.8 Ω USB Vbus connector D+ nearest D- 15.8 Ω device Gnd 143 Ω 143 Ω Data Sheet S16685EJ3V0DS µ PD720122 + 50-Ω To 50-Ω input of a Coax high-speed differential oscilloscope, ...
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DC characteristics of BIU Parameter Symbol Off-state output current I OZ Output short current I OS Input leakage current I I Output current, low I OL Output current, high I OH Output voltage, low V OL Output voltage, high ...
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Pin capacitance Parameter Symbol Input capacitance C IN Output/bidirectional capacitance C OUT Remark These are just estimated values. 2.5.4 Power consumption Parameter Symbol Power consumption Notes 1. SND PHY Reg. SPND ...
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AC Characteristics ( +70° The AC characteristics are classified into those of the USB interface block and those of the BIU. 2.6.1 Overall AC characteristics and those of BIU (1) Clock Parameter Symbol Clock ...
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AC characteristics of BIU block with Function 1 selected (1) CPU BUS read operation Symbol Parameter T1 Read cycle time T2 Address setup time (RDB↓) T3 Chip select setup time (RDB↓) T4 Buffer direction change time (RDB↓) T5 Output ...
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CPU bus write operation Symbol Parameter T11 Write cycle time T12 Address setup time (WRB↓) T13 Chip select setup time (WRB↓) T14 Write command width T15 Address hold time (WRB↑) T16 Chip select hold time (WRB↑) T17 WRB inactive ...
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CPU BUS RDB vs. WRB timing Symbol Parameter T20 WRB vs. RDB inactive time Remark It is assumed that the external pin capacitance (data bus = 50 pF). CPU bus read vs. write change timing CSB ...
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CPU bus DMA transfer (a) CPU bus DMA single mode read transfer timing Symbol Parameter T21 DMA request acknowledge setup time (RDB↓) T22 DMA request off time (EP1_DACKB↓) T23 DMA single mode read transfer cycle time T24 Read command ...
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EP1_DRQB EP1_DACKB RDB D15 to D0 EP1_TCB High level EP1_STOPB High level (End timing) EP1_DRQB EP1_DACKB Last − 1 RDB D15 to D0 EP1_TCB High level EP1_STOPB High level ...
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EP1_DRQB EP1_DACKB RDB EP1_TCB Data Sheet S16685EJ3V0DS µ PD720122 ...
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CPU bus DMA single mode write transfer Symbol Parameter DMA request acknowledge setup time (WRB ↓ ) T35 DMA request off time (EP2_DACKB ↓ ) T36 T37 DMA single mode write transfer cycle time T38 Write command width T39 ...
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EP2_DRQB EP2_DACKB WRB D15 to D0 EP2_TCB High level (End timing) EP2_DRQB EP2_DACKB WRB D15 to D0 EP2_TCB High level VALID t 36 ...
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EP2_DRQB EP2_DACKB WRB EP2_TCB Data Sheet S16685EJ3V0DS µ PD720122 29 ...
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CPU bus DMA demand read transfer timing Symbol Parameter DMA request acknowledge setup time (RDB ↓ ) T45 T46 DMA demand mode read transfer cycle time T47 Read command width T48 Read command inactive time Read data delay time ...
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EP1_DRQB EP1_DACKB RDB D15 to D0 EP1_TCB High level (End timing) EP1_DRQB EP1_DACKB Last − 1 RDB D15 to D0 EP1_TCB High level EP1_STOPB High level ...
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EP1_DRQB EP1_DACKB RDB EP1_TCB (Retransmission timing) DMA transfer retry timing If EP1_DACKB is deasserted without RDB access after EP1_DRQB has been deasserted, EP1_DRQB is asserted again. EP1_DRQB EP1_DACKB Last − 1 RDB D15 to D0 ...
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EP1_TCB is input when retransmission is executed) EP1_DRQB EP1_DACKB RDB EP1_TCB (One-cycle transfer) EP1_DRQB EP1_DACKB RDB D15 to D0 EP1_TCB High level EP1_STOPB ...
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CPU bus DMA demand write transfer timing Symbol Parameter T58 DMA request acknowledge setup time (WRB↓) T59 DMA demand mode write transfer cycle time T60 Write command width T61 Write command inactive time T62 Write data setup time (WRB↑) ...
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EP2_DRQB EP2_DACKB WRB D15 to D0 EP2_TCB High level (End timing) EP2_DRQB EP2_DACKB WRB D15 to D0 EP2_TCB VALID t 66 Last − 1 Last ...
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EP2_DRQB EP2_DACKB WRB EP2_TCB (Retransmission timing) DMA transfer retry timing If EP2_DACKB is deasserted without WRB access after EP2_DRQB has been deasserted, EP2_DRQB is asserted again. EP2_DRQB t 66 EP2_DACKB Last − 1 WRB ...
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EP1_TCB is input when retransmission is executed) EP2_DRQB EP2_DACKB WRB EP2_TCB Data Sheet S16685EJ3V0DS µ PD720122 37 ...
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CPU bus DMA read transfer vs. write transfer timing Symbol Parameter T68 RDB vs. WRB command inactive time Remark It is assumed that the external pin capacitance (data bus = 50 pF). EP1_DRQB Low level EP1_DACKB ...
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AC characteristics of BIU block with function selected (1) CPU bus read operation Symbol Parameter TB1 Read cycle time Address setup time (ALE ↓ ) TB2 Chip select setup time (ALE ↓ ) TB3 Read command ...
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CPU bus write operation Symbol Parameter TB13 Write cycle time Address setup time (ALE ↓ ) TB14 Chip select setup time (ALE ↓ ) TB15 Write command delay time (ALE ↓ ) TB16 Input data setup time (WRB ↑ ...
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External local bus (1) External local bus 16-bit mode (a) External local bus 16-bit mode DMA single mode read transfer timing Symbol Parameter DMA request acknowledge setup time (EP1_RDB ↓ ) L16T21 DMA request off time 1 (EP1_DACKB ↓ ...
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L16t 22 EP1_DRQB L16t 33 L16t 21 EP1_DACKB L16t L16t 24 25 EP1_RDB L16t 23 L16t L16t 26 LD15 to LD0 1 cycle L16t 27 EP1_TCB High level EP1_STOPB High level (Start timing) EP1_DRQB EP1_DACKB EP1_RDB LD15 to LD0 ...
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EP1_DRQB EP1_DACKB Last − 1 EP1_RDB LD15 to LD0 EP1_TCB High level EP1_STOPB High level (TCB timing) EP1_DRQB EP1_DACKB EP1_RDB EP1_TCB L16t 22 L16t Last VALID VALID L16t 31 L16T 22 L16T 21 L16T 29 L16T 30 Data ...
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External local bus 16-bit mode DMA single mode write transfer Symbol Parameter L16T35 DMA request acknowledge setup time (EP2_WRB↓) L16T36 DMA request off time 1 (EP2_DACKB↓) L16T37 DMA single mode write transfer cycle time L16T38 Write command width L16T39 ...
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EP2_DRQB EP2_DACKB L16t EP2_WRB LD15 to LD0 EP2_TCB High level (End timing) EP2_DRQB EP2_DACKB Last − 1 EP2_WRB L16t LD15 to LD0 EP2_TCB High level L16t 36 L16t 44 35 L16t 38 L16t 37 L16t L16t 40 41 ...
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EP2_DRQB EP2_DACKB EP2_WRB EP2_TCB 46 L16t 36 L16t 35 L16t L16t 42 43 Data Sheet S16685EJ3V0DS µ PD720122 ...
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External local bus 16-bit mode DMA demand read transfer timing Symbol Parameter DMA request acknowledge setup time (EP1_RDB ↓ ) L16T45 L16T46 DMA demand mode read transfer cycle time L16T47 Read command width L16T48 Read command inactive time Read ...
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EP1_DRQB EP1_DACKB L16t 46 L16t 45 L16t L16t 47 48 EP1_RDB L16t L16t 49 51 LD15 to LD0 1 cycle L16t 50 EP1_TCB High Level EP1_STOPB High Level (Start timing) EP1_DRQB EP1_DACKB EP1_RDB LD15 to LD0 EP1_TCB High level ...
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EP1_DRQB EP1_DACKB Last − 1 EP1_RDB LD15 to LD0 EP1_TCB High level EP1_STOPB High level (TCB timing) EP1_DRQB EP1_DACKB EP1_RDB EP1_TCB L16t 56 Last VALID VALID L16t 54 L16t 74 L16t 52 L16t 53 Data Sheet S16685EJ3V0DS µ ...
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DMA transfer retry timing If EP1_DACKB is deasserted without RDB access after EP1_DRQB has been deasserted, EP1_DRQB is asserted again. However, note that the retry operation cannot be performed in the 8-bit mode. EP1_DRQB L16t 56 EP1_DACKB Last ...
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EP1_DRQB EP1_DACKB EP1_RDB LD15 to LD0 High level EP1_TCB EP1_STOPB L16t 71 L16t L16t 45 47 L16t 49 L16t L16t 50 VALID L16t L16t 54 55 Data Sheet S16685EJ3V0DS µ PD720122 51 51 ...
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External local bus 16-bit mode DMA demand write transfer timing Symbol Parameter DMA request acknowledge setup time (EP2_WRB ↓ ) L16T58 L16T59 DMA demand mode write transfer cycle time L16T60 Write command width L16T61 Write command inactive time Write ...
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EP2_DRQB EP2_DACKB EP2_WRB LD15 to LD0 EP2_TCB High level (End timing) EP2_DRQB EP2_DACKB Last − 1 EP2_WRB LD15 to LD0 EP2_TCB High level L16t 58 L16t 59 L16t 60 L16t L16t L16t 63 62 VALID L16t 66 L16t ...
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EP2_DRQB EP2_DACKB EP2_WRB EP2_TCB (Retransmission timing) DMA transfer retry timing If EP2_DACKB is deasserted without RDB access after EP2_DRQB has been deasserted, EP2_DRQB is asserted again. However, note that the retry operation cannot be performed in the 8-bit ...
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EP1_TCB is input when retransmission is executed) EP2_DRQB EP2_DACKB EP2_WRB EP2_TCB (e) External local bus 16-bit mode DMA EP1_Read transfer vs. EP2_Write transfer timing Symbol Parameter L16T68 EP1_RDB vs. EP2_WRB command inactive time Remark It is assumed that the ...
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External local bus 8-bit mode (a) External local bus 8-bit mode DMA single mode read transfer timing Symbol Parameter DMA request acknowledge setup time (EP1_RDB ↓ ) L8T21 DMA request off time 1 (EP1_DACKB ↓ ) L8T22 L8T23 DMA ...
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EP1_DRQB EP1_DACKB EP1_RDB LD7 to LD0 L8t EP1_TCB High level (End timing) EP1_DRQB EP1_DACKB EP1_RDB LD7 to LD0 High level EP1_TCB High level EP1_STOPB L8t 22 L8t L8t 33 21 L8t 23 L8t 24 L8t 28 L8t 26 ...
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External local bus 8-bit mode DMA single mode write transfer Symbol Parameter DMA request acknowledge setup time (EP2_WRB ↓ ) L8T35 DMA request off time 1 (EP2_DACKB ↓ ) L8T36 L8T37 DMA single mode write transfer cycle time L8T38 ...
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EP2_DRQB EP2_DACKB EP2_WRB LD7 to LD0 EP2_TCB High level (End timing) EP2_DRQB EP2_DACKB Last − 1 EP2_WRB LD7 to LD0 EP2_TCB High level L8t 36 L8t 44 L8t 35 L8t 37 L8t 38 L8t 40 L8t 41 VALID ...
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External local bus 8-bit mode DMA demand read transfer timing Symbol Parameter DMA request acknowledge setup time (EP1_RDB ↓ ) L8T45 L8T46 DMA demand mode read transfer cycle time L8T47 Read command width L8T48 Read command inactive time Read ...
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EP1_DRQB EP1_DACKB EP1_RDB LD7 to LD0 EP1_TCB High level (End timing) EP1_DRQB EP1_DACKB Last − 1 EP1_RDB LD7 to LD0 EP1_TCB High level EP1_STOPB High level L8t 45 L8t L8t 47 48 L8t 49 L8t 51 L8t 50 ...
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External local bus 8-bit mode DMA demand write transfer timing Symbol Parameter L8T58 DMA request acknowledge setup time (EP2_WRB↓) L8T59 DMA demand mode write transfer cycle time L8T60 Write command width L8T61 Write command inactive time L8T62 Write data ...
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EP2_DRQB EP2_DACKB EP2_WRB LD7 to LD0 EP2_TCB High level (End timing) EP2_DRQB EP2_DACKB Last − 1 EP2_WRB LD7 to LD0 EP2_TCB L8t 58 L8t 59 L8t 60 L8t 62 VALID L8t 66 L8t Last L8t L8t 63 62 ...
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External local bus 8-bit mode DMA EP1_Read transfer vs. EP2_Write transfer timing Symbol Parameter L8T68 EP1_RDB vs. EP2_WRB command inactive time Remark It is assumed that the external pin capacitance (data bus = 50 pF). EP1_DRQB ...
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USB interface timing Parameter Full-speed source electrical characteristics Rise time Fall time Differential rise and fall time matching Full-speed data rate for hubs and devices that are high-speed capable Frame interval Consecutive frame interval jitter Source jitter total (including ...
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Parameter Device event timing Time from internal power good to device pulling D+/D− beyond V (min.) (signaling IHZ attach) Debounce interval provided by USB system software after attach Inter-packet delay (for low-/full-speed) Inter-packet delay for device response w/detachable cable for ...
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Figure 2-6. Transmit Waveform for Transceiver at D+/D− Level 1 Point 3 Point 1 Point 5 Level 2 Unit interval 0% Figure 2-7. Transmitter Measurement Fixtures Test supply voltage 15.8 Ω USB Vbus connector D+ nearest D– 15.8 Ω device ...
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Power-on and connection events Figure 2-8. Power-on and Connection Event Timing Hub port Attach detected power OK Hub port power-on ≥ 4. BUS V (min D− 100 ms T ∆t1 SIGATT (2) ...
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Figure 2-10. USB Differential-to-EOP Transition Skew and EOP Width for Full-Speed T PERIOD Crossover point Differential data lines Diff. Data-to- SE0 skew PERIOD xDEOP Data Sheet S16685EJ3V0DS µ PD720122 Crossover point extended Source EOP width: ...
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Figure 2-11. USB Receiver Jitter Tolerance for Full-Speed T PERIOD Differential data lines (3) USB connection sequence on USB1.1 bus The PHY core implemented on the Check the SP_MODE bit (SP_MODE) of the Int Status 2 register after an EPC2_STG ...
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USB connection sequence on USB 2.0 bus Figure 2-13. USB Connection Sequence on USB 2.0 Bus Pull-up is active. USB bus HDS t FCA T 0 USBRST SPMODE (5) Bus reset sequence (1) The bus reset ...
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Bus reset sequence (2) The bus reset sequence when connected to a USB 2.0 bus is shown below. Pull-up is inactive Reversion to full-speed mode High-speed packet USB bus t t SPD CSR t FCA T 0 USBRST SPMODE ...
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USB reset from suspend state (1) Figure 2-16. USB Reset from Suspend State (1) Pull-up is active. USB bus SCA T 0 USB_RST SPMODE (8) USB reset from suspend state (2) Figure 2-17. USB Reset from ...
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Suspend and resume on USB1.1 bus Figure 2-18. Suspend and Resume on USB 1.1 Bus FS EOP USB bus t SPD SPNDOUT SUSPEND RSUMOUT SPMODE High Current source and PLL, etc. are disabled. t ...
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Suspend and resume on USB2.0 bus Figure 2-19. Suspend and Resume on USB 2.0 Bus Reversion to full-speed mode High-speed packet USB bus t t SPD CSR t SUS T 0 SPNDOUT SUSPEND RSUMOUT Low SPMODE (11) Remote wakeup ...
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Remote wakeup on USB2.0 Figure 2-21. Remote Wakeup on USB 2.0 Reversion to full-speed mode High-speed packet USB bus t t SPD CSR T 0 SPNDOUT SUSPEND RSUMOUT RSUMIN Low SPEEDMODE SUS t ...
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PACKAGE DRAWING µ • PD720122GC-9EU, 720122GC-9EU-A 100-PIN PLASTIC TQFP (FINE PITCH) (14x14 100 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition ...
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PD720122F1-DN2, 720122F1-DN2-A 109-PIN PLASTIC FBGA (11x11) D INDEX MARK φ φ Data ...
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RECOMMENDED SOLDERING CONDITIONS µ The PD720122 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact your NEC Electronics sales representative. For technical information, see the following website. ...
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Table 4-1. Recommended Soldering Conditions of Surface-Mount Type (2/2) • µ PD720122F1-DN2: 109-pin plastic FBGA (11 × 11) Soldering Method Infrared ray reflow Peak package’s surface temperature: 235° C, Reflow time: 30 seconds or less (210 °C or higher), Maximum ...
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Data Sheet S16685EJ3V0DS µ PD720122 81 ...
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Data Sheet S16685EJ3V0DS µ PD720122 ...
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NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care ...
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EEPROM is a trademark of NEC Electronics Corporation. USB logo is a trademark of USB Implementers Forum, Inc. • The information in this document is current as of March, 2005. The information is subject to change without notice. For actual ...