ISP1160BM,518 NXP Semiconductors, ISP1160BM,518 Datasheet - Page 35

• Manufacturer Part Number: ISP1160BM,518
• Manufacturer: NXP Semiconductors

Specifications of ISP1160BM,518

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Package Type: PQFP
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

10. HC registers
Table 7.
ISP1160-01_7
Product data sheet
Read
00
01
02
03
04
05
Address (Hex)
Write
N/A
81
82
83
84
85
HC registers summary
9.9.2.2 Wake-up by pin CS_N (software wake-up)
9.9.2.3 Wake-up by USB devices
Register
HcRevision
HcControl
HcCommandStatus
HcInterruptStatus
HcInterruptEnable
HcInterruptDisable
During the USBSuspend state, an external microprocessor issues a chip select signal
through pin CS_N to the ISP1160/01. This method of access to the ISP1160/01 internal
registers is a software wake-up.
For the USB bus resume, a USB device attached to the root hub port issues a resume
signal to the HC through the USB bus, switching the HC from the USBSuspend state to
the USBResume state. This will also set bit ResumeDetected of the HcInterruptStatus
register (03H to read, 83H to write).
No matter which method is used to wake up the HC from the USBSuspend state, the
corresponding interrupt bits must be enabled before the HC goes into the USBSuspend
state so that the microprocessor can receive the correct interrupt request to wake up the
HC.
The HC contains a set of on-chip control registers. These registers can be read or written
by the Host Controller Driver (HCD). The Control and Status register sets, Frame Counter
register sets, and Root Hub register sets are grouped under the category of HC
Operational registers (32 bits). These operational registers are made compatible to
OpenHCI (Host Controller Interface) operational registers. This allows the OpenHCI HCD
to be easily ported to the ISP1160/01.
Reserved bits may be defined in future releases of this specification. To ensure
interoperability, the HCD must not assume that a reserved field contains logic 0.
Furthermore, the HCD must always preserve the values of the reserved field. When a
R/W register is modified, the HCD must first read the register, modify the bits desired, and
then write the register with the reserved bits still containing the original value.
Alternatively, the HCD can maintain an in-memory copy of previously written values that
can be modified and then written to the HC register. When a ‘write to set’ or ‘clear the
register’ is performed, bits written to reserved fields must be logic 0.
As shown in
operational registers are similar to the offsets defined in the OHCI specification with the
addresses being equal to offset divided by 4.
Table
7, the addresses (the commands for reading registers) of these 32-bit
Rev. 07 — 29 September 2009
32
Width Reference
32
32
32
32
32
Section 10.1.1 on page 36
Section 10.1.2 on page 37
Section 10.1.3 on page 38
Section 10.1.4 on page 39
Section 10.1.5 on page 40
Section 10.1.6 on page 42
Embedded USB host controller
Functionality
HC control and status registers
ISP1160/01
© ST-ERICSSON 2009. All rights reserved.
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