ISP1160BM,518 NXP Semiconductors, ISP1160BM,518 Datasheet - Page 43

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ISP1160BM,518

Manufacturer Part Number
ISP1160BM,518
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of ISP1160BM,518

Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Package Type
PQFP
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
Table 20.
ISP1160-01_7
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcFmInterval register: bit allocation
10.2.1 HcFmInterval register (R/W: 0DH/8DH)
10.2 HC frame counter registers
R/W
R/W
R/W
R/W
FIT
31
23
15
0
0
0
7
1
reserved
Table 19.
The HcFmInterval register contains a 14-bit value which indicates the bit time interval in a
frame (that is, between two consecutive SOFs), and a 15-bit value indicating the
full-speed maximum packet size that the HC may transmit or receive without causing a
scheduling overrun. The HCD may carry out minor adjustments on the FrameInterval by
writing a new value at each SOF. This allows the HC to synchronize with an external clock
resource and to adjust any unknown clock offset.
Code (Hex): 0D — read
Code (Hex): 8D — write
Bit
5
4
3
2
1
0
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
1
HcInterruptDisable register: bit description
Symbol
FNO
UE
RD
SF
-
SO
R/W
R/W
R/W
R/W
29
21
13
0
0
1
5
0
Rev. 07 — 29 September 2009
Description
0 — ignore
1 — disable interrupt generation due to Frame Number Overflow
0 — ignore
1 — disable interrupt generation due to Unrecoverable Error
0 — ignore
1 — disable interrupt generation due to Resume Detect
0 — ignore
1 — disable interrupt generation due to Start of Frame
reserved
0 — ignore
1 — disable interrupt generation due to Scheduling Overrun
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
1
FSMPS[7:0]
FI[7:0]
FSMPS[14:8]
R/W
R/W
R/W
R/W
27
19
11
0
0
1
3
1
FI[13:8]
…continued
Embedded USB host controller
R/W
R/W
R/W
R/W
26
18
10
0
0
1
2
1
ISP1160/01
© ST-ERICSSON 2009. All rights reserved.
R/W
R/W
R/W
R/W
25
17
0
0
9
1
1
1
R/W
R/W
R/W
R/W
24
16
0
0
8
0
0
1
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