AM53CF96KC/W AMD (ADVANCED MICRO DEVICES), AM53CF96KC/W Datasheet - Page 28

• Manufacturer Part Number: AM53CF96KC/W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM53CF96KC/W

• Lead Free Status / RoHS Status: Not Compliant

Current FIFO/Internal State Register (07H) Read
This register has two fields, the Current FIFO field and
the Internal State field.
CFISREG – Bits 7:5 – IS 2:0 – Internal State 2:0
The Internal State Register (ISREG) tracks the progress
of a sequence-type command.
The IS 2:0 bits are duplicated from the IS 2:0 field in the
Internal State Register (ISREG) in the normal mode. If
the device is in the test mode, (see CNTLREG1, bit 3)
IS 0 is set to indicate that the offset value is non-zero.
A non-zero value indicates that synchronous data
Synchronous Offset Register (07H) Write
The Synchronous Offset Register (SOFREG) controls
REQ/ACK deassertion/assertion delay and stores a
4-bit count of the number of bytes that can be sent to
(or received from) the SCSI bus during synchronous
transfers without an ACK (or REQ). Bytes exceeding
the threshold will be sent one byte at a time
(asynchronously). That is, each byte will require an
ACK/REQ handshake. To set up an asynchronous
transfer, the SOFREG is set to zero. The SOFREG is set
to zero after a hard or soft reset.
28
AMD
Current FIFO/Internal State Register
CFISREG
Synchronous Offset Register
SOFREG
RAD1
IS2
7
0
7
0
RAD0
IS1
6
0
6
0
RAA1
IS0
5
0
5
0
Am53CF94/Am53CF96
RAA0
CF4
4
0
4
0
SO3
CF3
3
3
0
0
transfer can continue. A zero value indicates that the
synchronous offset count has been reached and no
more data can be transferred until an acknowledge is
received.
CFISREG – Bits 4:0 – CF 4:0 – Current FIFO 4:0
The CF 4:0 bits are the binary coded value of the num-
ber of bytes in the FIFO. These bits should not be read
when the device is transferring data since this count
may not be stable.
SO2
SOFREG – Bits 7:6 – RAD 1:0
These bits may be programmed to control the deasser-
tion delay of the REQ and ACK signals during synchro-
nous transfers. Deassertion delay is expressed as input
clock cycles, and depends on the implementation of
FASTCLK. (See CNTLREG3, bit 3)
CF2
2
0
2
0
CF1
SO1
1
0
1
0
Address: 07
Address: 07
Type: Read
Type: Write
CF0
SO0
0
0
0
0
H
H
Current FIFO 4:0
Internal State 2:0
Synchronous Offset 3:0
REQ/ACK Deassertion 1:0
REQ/ACK Assertion 1:0
17348B-26
17348B-27