AM53CF96KC/W AMD (ADVANCED MICRO DEVICES), AM53CF96KC/W Datasheet - Page 29

• Manufacturer Part Number: AM53CF96KC/W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM53CF96KC/W

• Lead Free Status / RoHS Status: Not Compliant

SOFREG – Bits 5:4 – RAA 1:0
These bits may be programmed to control the assertion
delay of the REQ and ACK signals during synchronous
transfers. Unlike deassertion delay, assertion delay is
independent of the FASTCLK setting.
Control Register One (08H) Read/Write
The Control Register 1 (CNTLREG1) sets up the device
with various operating parameters.
CNTLREG1 – Bit 7 – ETM – Extended Timing Mode
Enabling this feature will increase the minimum setup
time for data being transmitted on the SCSI bus. This bit
should only be set if the external cabling conditions pro-
duce SCSI timing violations. FASTCLK operation is
unaffected by this feature.
CNTLREG1 – Bit 6 – DISR – Disable Interrupt on
SCSI Reset
The DISR bit masks the reporting of the SCSI reset.
When the DISR bit is set and a SCSI reset is asserted,
the device will disconnect from the SCSI bus and remain
idle without interrupting the host processor. When the
DISR bit is reset and a SCSI reset is asserted the device
will respond by interrupting the host processor. The
DISR bit is reset to zero by a hard or soft reset.
SOFREG FASTCLK
Bits 7:6 Ctrl 3, Bit 3
00
01
10
11
00
01
10
11
0
0
0
0
1
1
1
1
Control Register One
CNTLREG1
ETM
7
0
Deassertion Delay
REQ/ACK
Input CLK Cycles
Default – 0 cycles
1/2 cycle early
1 cycle delay
1/2 cycle delay
Default – 0 cycles
1/2 cycle delay
1 cycle delay
1 1/2 cycles delay
DISR
6
0
PTE
5
0
PERE
4
0
Am53CF94/Am53CF96
STE
3
0
CID2
2
x
SOFREG – Bits 3:0 – SO 3:0 – Synchronous
Offset 3:0
The SO 3:0 bits are the binary coded value of the num-
ber of bytes that can be sent to (or received from) the
SCSI bus without an ACK (or REQ) signal. A zero value
designates Asynchronous xfer, while a non-zero value
designates the number of bytes for synchronous
transfer.
CNTLREG1 – Bit 5 – PTE – Parity Test Enable
The PTE bit is for test use only. When the PTE bit is set
the parity on the output (SCSI or host processor) bus is
forced to the value of the MSB (bit 7) of the output data
from the internal FIFO. This allows parity errors to be
created to test the hardware and software. The PTE bit
is reset to zero by a hard or soft reset. This bit should not
be set in normal operation.
CNTLREG1 – Bit 4 – PERE – Parity Error Report-
ing Enable
The PERE bit enables the checking and reporting of par-
ity errors on incoming SCSI bytes during the information
transfer phase. When the PERE bit set and bad parity is
detected, the PE bit in the STATREG is will be set but an
interrupt will not be generated. In the Initiator mode the
ATN signal will also be asserted on the SCSI bus. When
Type: Read/Write
CID1
1
SOFREG
x
Address: 08
Bits 5:4
00
01
10
11
CID0
0
x
H
Chip ID 2:0
Self Test Enable
Parity Error Reporting Enable
Parity Test Enable
Disable Interrupt on SCSI Reset
Extended Timing Mode
Assertion Delay
REQ/ACK
Input CLK Cycles
Default – 0 cycles
1/2 cycle delay
1 cycle delay
1 1/2 cycles delay
17348B-28
AMD
29