STPCI2HEYCE STMicroelectronics, STPCI2HEYCE Datasheet - Page 51

• Manufacturer Part Number: STPCI2HEYCE
• Manufacturer: STMicroelectronics

Specifications of STPCI2HEYCE

• Lead Free Status / RoHS Status: Compliant

4.5.3. SDRAM INTERFACE
Figure
characteristics of the SDRAM interface. The
Figure 4-5. SDRAM Timing Diagram
Table 4-10. SDRAM Bus AC Timings - Commercial Temperature Range
The PC100 memory is recommended to reach 90MHz operation.
Note: These timings are for a load of 50pF, part running at 100MHz and ReadCLK activated and set to 0
Toutput
Tsetup
Tcycle
Tdelay
MCLKx
MCLKI
STPC.output
STPC.input
Name
Thigh
Thold
Tlow
4-5,
Table
Parameter
MCLKI Cycle Time
MCLKI High Time
MCLKI Low Time
MCLKI Rising Time
MCLKI Falling Time
MCLKx to MCLKI delay
MCLKI to RAS# Valid
MCLKI to CAS# Valid
MCLKI to CS# Valid
MCLKI to DQM[ ] Outputs Valid
MCLKI to MD[ ] Outputs Valid
MCLKI to MA[ ] Outputs Valid
MCLKI to MWE# Valid
MD[63:0] setup to MCKLI
MD[63:0] hold from MCKLI
4-10,
Thold
Table 4-11
Tdelay
lists the AC
Toutput (max)
Thigh
MCLKx clocks are the input clock of the SDRAM
devices.
Tcycle
Tsetup
Toutput (min)
Tlow
-0.36
1.35
1.35
Min
0.5
1.6
4.7
1.6
1.6
1.6
1.6
11
4
4
Typ
1
STPC® ATLAS
Max
1.5
5.2
5.2
5.2
5.2
5.2
5.2
5.2
2.3
1
1
Unit
51/108
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1