STPCI2HEYCE STMicroelectronics, STPCI2HEYCE Datasheet - Page 83

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STPCI2HEYCE

Manufacturer Part Number
STPCI2HEYCE
Description
Manufacturer
STMicroelectronics
Datasheet

Specifications of STPCI2HEYCE

Lead Free Status / RoHS Status
Compliant

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The
implementation of the external glue logic for DMA
Request time-multiplexing and DMA Acknowledge
demultiplexing. Like for the interrupt lines, this
Figure 6-12. Typical DMA multiplexing and demultiplexing
ISA, Refresh
ISA, PIO
ISA, FDC
ISA, PIO
Slave DMAC
ISA
ISA
ISA
figure
below
describes
ISA_CLK2X
ISA_CLK
DMA_ENC[0]
DMA_ENC[1]
DMA_ENC[2]
a
complete
DRQ[0]
DRQ[1]
DRQ[2]
DRQ[3]
DRQ[4]
DRQ[5]
DRQ[6]
DRQ[7]
logic can be simplified when only few DMA
channels are used in the application.
This glue logic is not needed in Local bus mode as
it does not support DMA transfers.
1C0
1C1
1C2
1C3
2C0
2C1
2C2
2C3
A
B
A
B
C
G1
G2A
74x153
74x138
1G
G2B
2G
Y0#
Y1#
Y2#
Y3#
Y4#
Y5#
Y6#
Y7#
1Y
2Y
DACK0#
DACK1#
DACK2#
DACK3#
DACK5#
DACK6#
DACK7#
STPC® ATLAS
DREQ_MUX[0]
DREQ_MUX[1]
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