MC9S08AW60CFGE Freescale, MC9S08AW60CFGE Datasheet - Page 234
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MC9S08AW60CFGE
Manufacturer Part Number
MC9S08AW60CFGE
Description
Manufacturer
Freescale
Datasheet
1.MC9S08AW60CFGE.pdf
(336 pages)
Specifications of MC9S08AW60CFGE
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
40MHz
Interface Type
I2C/SCI/SPI
Total Internal Ram Size
2KB
# I/os (max)
34
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
LQFP
Program Memory Type
Flash
Program Memory Size
60KB
Lead Free Status / RoHS Status
Compliant
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MC9S08AW60CFGE
Manufacturer:
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Quantity:
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Inter-Integrated Circuit (S08IICV2)
In slave mode, the same functions are available after an address match has occurred.
The TX bit in IIC1C must correctly reflect the desired direction of transfer in master and slave modes for
the transmission to begin. For instance, if the IIC is configured for master transmit but a master receive is
desired, reading the IIC1D does not initiate the receive.
Reading the IIC1D returns the last byte received while the IIC is configured in master receive or slave
receive modes. The IIC1D does not reflect every byte transmitted on the IIC bus, nor can software verify
that a byte has been written to the IIC1D correctly by reading it back.
In master transmit mode, the first byte of data written to IIC1D following assertion of MST is used for the
address transfer and should comprise of the calling address (in bit 7 to bit 1) concatenated with the required
R/W bit (in position bit 0).
13.3.6
234
AD[10:8]
Reset
GCAEN
ADEXT
Field
DATA
Field
7–0
2–0
7
6
W
R
GCAEN
IIC Control Register 2 (IIC1C2)
Data — In master transmit mode, when data is written to the IIC1D, a data transfer is initiated. The most
significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data.
General Call Address Enable. The GCAEN bit enables or disables general call address.
0 General call address is disabled
1 General call address is enabled
Address Extension. The ADEXT bit controls the number of bits used for the slave address.
0 7-bit address scheme
1 10-bit address scheme
Slave Address. The AD[10:8] field contains the upper three bits of the slave address in the 10-bit address
scheme. This field is only valid when the ADEXT bit is set.
0
7
When transitioning out of master receive mode, the IIC mode should be
switched before reading the IIC1D register to prevent an inadvertent
initiation of a master receive data transfer.
= Unimplemented or Reserved
ADEXT
0
6
Figure 13-8. IIC Control Register (IIC1C2)
Table 13-8. IIC1C2 Field Descriptions
Table 13-7. IIC1D Field Descriptions
MC9S08AC16 Series Data Sheet, Rev. 8
0
0
5
NOTE
0
0
4
Description
Description
3
0
0
AD10
0
2
Freescale Semiconductor
AD9
0
1
AD8
0
0
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