MC9S08AW60CFGE Freescale, MC9S08AW60CFGE Datasheet - Page 84

• Manufacturer Part Number: MC9S08AW60CFGE
• Manufacturer: Freescale

Specifications of MC9S08AW60CFGE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 34
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

Chapter 6 Parallel Input/Output
6.3.2
Port B pins are general-purpose I/O pins. Parallel I/O function is controlled by the port B data (PTBD) and
data direction (PTBDD) registers which are located in page zero register space. The pin control registers,
pullup enable (PTBPE), slew rate control (PTBSE), and drive strength select (PTBDS) are located in the
high page registers. Refer to
general-purpose I/O control and
Port B general-purpose I/O are shared with the ADC and TPM3 timer channels. Any pin enabled as an
ADC input will have the general-purpose I/O function disabled. When any TPM3 function is enabled, the
direction (input or output) is controlled by the TPM3 and not by the data direction register of the parallel
I/O port. Refer to
as TPM channels. Refer to
information about using port B as analog inputs.
6.3.3
Port C pins are general-purpose I/O pins. Parallel I/O function is controlled by the port C data (PTCD) and
data direction (PTCDD) registers which are located in page zero register space. The pin control registers,
pullup enable (PTCPE), slew rate control (PTCSE), and drive strength select (PTCDS) are located in the
high page registers. Refer to
general-purpose I/O control and
Port C general-purpose I/O is shared with SCI2, IIC, and MCLK. When any shared function is enabled,
the direction, input or output, is controlled by the shared function and not by the data direction register of
the parallel I/O port. Also, for pins which are configured as outputs by the shared function, the output data
is controlled by the shared function and not by the port data register.
Refer to
port C pins as SCI pins.
Refer to
as IIC pins.
Refer to
PTC2 as the MCLK pin.
84
Port B
Port C
Chapter 11, “Serial Communications Interface
Chapter 13, “Inter-Integrated Circuit
Chapter 5, “Resets, Interrupts, and System
Port B
Port C
MCU Pin:
MCU Pin:
Chapter 10, “Timer/PWM
Bit 7
R
Bit 7
Chapter 14, “Analog-to-Digital Converter
0
Section 6.4, “Parallel I/O
Section 6.4, “Parallel I/O
Section 6.5, “Pin
Section 6.5, “Pin
MC9S08AC16 Series Data Sheet, Rev. 8
R
6
R
6
Figure 6-3. Port B Pin Names
Figure 6-4. Port C Pin Names
(S08TPMV3),” for more information about using port B pins
PTC5/
RxD2
R
(S08IICV2)” for more information about using port C pins
5
5
Control” for more information about pin control.
Control” for more information about pin control.
Configuration” for more information about using
Control” for more information about
Control” for more information about
PTC4
R
(S08SCIV4)” for more information about using
4
3
TPM3CH0/
AD1P3
PTB3/
PTC3/
TxD2
3
3
(S08ADC10V1)” for more
TPM3CH1/
PTC2/
MCLK
AD1P2
PTB2/
2
2
Freescale Semiconductor
PTC1/
SDA1
AD1P1
PTB1/
1
1
PTC0/
SCL1
AD1P0
Bit 0
PTB0/
Bit 0