MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 456

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
“MSCAN Control Register 0
stamp after the respective transmit buffer has been flagged empty.
The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer
overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The
CPU can only read the time stamp registers.
Read: Anytime when TXEx flag is set (see
(CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see
“MSCAN Transmit Buffer Selection Register
Write: Unimplemented
10.4
10.4.1
This section provides a complete functional description of the MSCAN. It describes each of the features
and modes listed in the introduction.
456
Reset:
Reset:
W
W
Functional Description
R
R
General
TSR15
TSR7
x
x
7
7
Figure 10-37. Time Stamp Register — High Byte (TSRH)
Figure 10-38. Time Stamp Register — Low Byte (TSRL)
TSR14
TSR6
6
x
6
x
(CANCTL0)”). In case of a transmission, the CPU can only read the time
MC9S12XDP512 Data Sheet, Rev. 2.21
TSR13
TSR5
5
x
5
x
Section 10.3.2.7, “MSCAN Transmitter Flag Register
(CANTBSEL)”).
TSR12
TSR4
4
x
4
x
TSR11
TSR3
3
x
3
x
TSR10
TSR2
x
x
2
2
Freescale Semiconductor
TSR9
TSR1
Section 10.3.2.11,
x
x
1
1
TSR8
TSR0
x
x
0
0