MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 546
MC9S12XDT512CAA
Manufacturer Part Number
MC9S12XDT512CAA
Description
Manufacturer
Freescale
Datasheet
1.MC9S12XDT512CAA.pdf
(1348 pages)
Specifications of MC9S12XDT512CAA
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
40MHz
Interface Type
CAN/I2C/SCI/SPI
Total Internal Ram Size
32KB
# I/os (max)
59
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/3.15V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
PQFP
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant
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Chapter 13 Periodic Interrupt Timer (S12PIT24B4CV1)
13.3.0.2
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
13.3.0.3
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
546
PFLT[3:0]
PCE[3:0]
Reset
Reset
Field
Field
3:0
3:0
W
W
R
R
PIT Force Load Bits for Timer 3-0 — These bits have only an effect if the corresponding timer channel (PCE
set) is enabled and if the PIT module is enabled (PITE set). Writing a one into a PFLT bit loads the corresponding
16-bit timer load register into the 16-bit timer down-counter. Writing a zero has no effect. Reading these bits will
always return zero.
PIT Enable Bits for Timer Channel 3:0 — These bits enable the PIT channels 3-0. If PCE is cleared, the PIT
channel is disabled and the corresponding flag bit in the PITTF register is cleared. When PCE is set, and if the
PIT module is enabled (PITE = 1) the 16-bit timer counter is loaded with the start count value and starts
down-counting.
0 The corresponding PIT channel is disabled.
1 The corresponding PIT channel is enabled.
PIT Force Load Timer Register (PITFLT)
PIT Channel Enable Register (PITCE)
0
0
0
0
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
0
0
0
0
6
6
Figure 13-4. PIT Force Load Timer Register (PITFLT)
Figure 13-5. PIT Channel Enable Register (PITCE)
Table 13-2. PITFLT Field Descriptions
Table 13-3. PITCE Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
0
0
5
5
0
0
0
0
4
4
Description
Description
PFLT3
PCE3
0
0
0
3
3
PFLT2
PCE2
0
0
0
2
2
Freescale Semiconductor
PFLT1
PCE1
0
0
0
1
1
PFLT0
PCE0
0
0
0
0
0
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