QG80333M500 S L9BH Intel, QG80333M500 S L9BH Datasheet - Page 10

• Manufacturer Part Number: QG80333M500 S L9BH
• Manufacturer: Intel

Specifications of QG80333M500 S L9BH

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Intel® 80333 I/O Processor
Summary Table of Changes
Specification Clarifications (Sheet 1 of 2)
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Status
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PCI Express* to PCI-X Bridge does not support Device ID Messaging (DIM)
64 MB and 2 GB DDR333 capacities not tested in post-silicon validation
DDR-II 400 unbuffered DIMMs are not supported
Memory map for 2 GByte of DDR memory
PCI configuration write anomaly when clearing BINIT[1]
PWRGD and PERST# are the same signals
Back-to-back MCU MMR reads
Reserved IDSELs on A-segment
Retry Disable Sequence
Write requirements for the Peripheral Bus Interface
PCI-X Status Register during PCI mode
M_RST# driven to DDR-II or DDR-I voltage levels
BIU master abort causes two interrupts on reads
Potential race condition with Interrupt Controller Unit status bits
Reset Internal Bus (PCSR[5]) usage
PCI Express* Transaction Header Log register repeats on offset 124 and 128
SHPC sequence
Bus Interface Unit follows PCI ordering rules
UART, I2C and GPIO memory mapped registers should be addressed with
32-bit accesses
UART Interrupt Identification Register
Reads on 16-bit PBI bus operate as 32-bit
3.3 V to 1.5 V leakage
Accessing extended bridge configuration space from the Intel XScale®
processor
Recommended B-segment termination when using the 80333 on PCI Express*
adapter cards
B-segment arbiter might not park on the last master when in PCI-X 133 MHz
mode
Configuring XINTx# signals as PCI interrupts
Power plane isolation for Battery Back-Up (BBU) mode
AAU result can be written directly to PCI host memory
SMBus connection recommendations for PCI Express* adapter cards
PBI lockout condition
PFREQ functionality
PWRDELAY functionality during power sequencing
HPI# (High Priority Interrupt) is a maskable interrupt
Specification Clarifications
Specification Update