QG80333M500 S L9BH Intel, QG80333M500 S L9BH Datasheet - Page 40

• Manufacturer Part Number: QG80333M500 S L9BH
• Manufacturer: Intel

Specifications of QG80333M500 S L9BH

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Intel® 80333 I/O Processor
Specification Clarifications
23.
Issue:
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40
Accessing extended bridge configuration space from the Intel XScale
processor
In certain cases, the Intel XScale
of the bridge headers (for example, see Non-Core Erratum 22,
PCI Express* Flow Control Protocol Error Severity bit” on page
processor issues the configuration cycle address using OCCAR, bits[27:24] can be used for
addressing the extended space. For example, to access offset 10Ch of A-bridge configuration
space, use an address of 0x0101.000C for a type-zero configuration cycle.
No
Recommended B-segment termination when using the 80333 on
PCI Express* adapter cards
For PCI Express* adapter cards, the B-segment is not used. Assuming PCIODTEN = 1 to enable
internal pull-ups, the following external connections must be made for an unused B-segment:
No
B-segment arbiter might not park on the last master when in PCI-X 133 MHz
mode
When the B-segment is running in PCI-X 133 MHz mode, the arbiter might not park on the last
master, when bit[8] of the Internal Arbiter Control register (ARB_CNTRL[8], offset 16Ah) is
cleared.
This happens only when the B-segment is running at 133 MHz. When running at 66 MHz or
100 MHz, the arbiter parks the bus on the last master when ARB_CNTRL[8] is cleared. The
A-segment does not exhibit this behavior with the same setup.
No
Configuring XINTx# signals as PCI interrupts
The PCI Specification Rev. 2.3 states that PCI interrupts are defined as “level sensitive” and “active
low”.
To configure the XINTx# signals of the 80333 as “level sensitive”, APIC_RDLxx[15] (Trigger
Mode) must be changed to 1 from its default of 0.
To configure the XINTx# signals of the 80333 as “active low”, APIC_RDLxx[13] (Interrupt Input
Pin Polarity) must be changed to 1 from its default of 0.
No
1. Connect B_CLKOUT to B_CLKIN. The other clockouts can be turned off by software (PCI
2. For B_PME#, use an 8.2 KΩ pull-up.
3. For B_PCIXCAP, use a 3.3 KΩ pull-up.
4. For B_RCOMP, use 100 Ω to ground.
Fix. See the
Fix. See the
Fix. See the
Fix. See the
Clock Control register at offset 43 in the B-segment bridge configuration space).
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
®
processor might need to access the extended configuration space
7.
7.
7.
7.
21). When the Intel XScale
“Incorrect default value for
Specification Update
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