QG80333M500 S L9BH Intel, QG80333M500 S L9BH Datasheet - Page 26

• Manufacturer Part Number: QG80333M500 S L9BH
• Manufacturer: Intel

Specifications of QG80333M500 S L9BH

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Intel® 80333 I/O Processor
Non-Core Errata
35.
Problem:
Implication:
Workaround:
Status:
36.
Problem:
Implication:
Workaround:
Status:
26
Internal Clock Misalignment Can Cause Processor Hang
After a reset, the 80333 can hang during initial accesses to SDRAM, due to a possible clock
misalignment, aggravated by a race condition in the clock divider clear circuit.
A failure will manifest itself as a hang of the I/O processor after reset, during initial accesses to
SDRAM. Subsequent warm or cold resets may clear the condition and allow the 80333 to continue
operation.
In most cases, doing a cold or warm reset will clear this condition. Increasing the 1.5v power
supply will reduce the probability of a processor hang. Intel is screening parts to eliminate the
probability of occurrence (refer to
page
Fixed. This issue was fixed in the A-1 stepping of the product (this is also related to
“Internal Clock Misalignment” on page
page
Spurious DMA0 End-Of-Transfer Interrupt
When the interrupt controller goes from having no interrupts asserted to one or more asserted, there
is a 1-clock cycle window in which the IINTVEC (IRQ Interrupt Vector register; FFFF_E7C8h or
CP6, register 14) or FINTVEC (FIQ Interrupt Vector register; FFFF_E7CCh or CP6, register 15)
may report the value of the INTBASE register (Interrupt Base register; FFFF_E7C0h or CP6,
register 12), which is the vector address for interrupt 0, DMA0 End-of-Transfer.
This condition can occur even if the DMA0 EOT interrupt is masked, INTCTL0.0 = 0.
No negative impact expected. If the routine that reads the IINTVEC/FINTVEC qualifies the return
value against IINTSRC0.0/FINTSRC0.0, it will either see there is nothing to do or it will validly
call the DMA0 End-of-Transfer handler.
If IINTVEC/FINTVEC equals INTBASE, then re-read the IINTVEC/FINTVEC register.
No
Fix. Not to be fixed. See the
32).
7.
Table , “Summary Table of Changes” on page
Specification Change #6, “Internal Clock Misalignment” on
32). See the
Table , “Summary Table of Changes” on
Specification Update
7.
Section 6,