QG80333M500 S L9BH Intel, QG80333M500 S L9BH Datasheet - Page 17

• Manufacturer Part Number: QG80333M500 S L9BH
• Manufacturer: Intel

Specifications of QG80333M500 S L9BH

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

9.
Problem:
Implication:
Workaround:
Status:
10.
Problem:
Implication:
Workaround:
Status:
Specification Update
ATU passing rules operation in PCI mode
When the A-segment bus is in PCI bus mode, the PCI passing rule enforcement logic within the
ATU allows a read completion to pass write data, until at least four inbound delayed reads, inbound
configuration writes, inbound configuration reads, or any combination of these have occurred from
the PCI bus.
This issue causes a deadlock condition in legacy devices that contain shared read and write data
queues, where the device allocates the data buffer for the requested delayed read data and is also
being addressed by the outbound ATU write data.
This ATU functionality does not exist in PCI-X mode.
Use the A-segment bus in PCI-X mode.
When the A-segment bus is in PCI mode, configuration retry is enabled, and the legacy buffer
allocating device is present in the system, the ATU must not issue writes to that device until the
configuration cycles or reads have completed. When this situation cannot be achieved by the host,
the ATU can be momentarily programmed in loopback mode and issue delayed reads to itself.
This workaround is required only when the ATU is sending upstream traffic at the same time as the
host is configuring it. This should not happen since the ATU needs to wait for the driver to be
enabled after enumeration completes.
This erratum does not occur when configuration retry is deasserted at power-on and the host meets
the above configuration cycles.
No
Secondary bus PCI RST# pulse prior to the rising edge of PWRGD
During system power-on and prior to the 80333 receiving the rising edge of PWRGD, a pulse is
observed on the secondary bus PCI RST# signals.
This functionality is a result of the 3.3v to 1.5v leakage described in Specification Clarification 22.
Other signals that may see a pulse during power-on include the following: all Peripheral Bus
Interface (PBI), PCI, GPIO, UART, JTAG and PWRDELAY signals. Refer to Specification
Clarification
I2C.
PCI/PCI-X controllers on the secondary bus segments might interpret this PCI RST# pulse as a true
rising edge and initialize into an undetermined state. Pulses on PWE# and PCEx# may cause data
corruption for memory devices connected to the PBI bus.
A hardware workaround has been identified. Use the PWRGD signal that is received by the 80333
to gate the secondary bus PCI RST# signals. For example, use PWRGD and A_RST# as inputs to
an AND gate and connect the output to the secondary device RST# pin. The gate delay must be
kept down to ~2 ns, so as to not interfere with the PCI initialization pattern.
Another workaround is to bring up 3.3 V and 1.5 V power rails simultaneously, but continue to
maintain the power-sequencing requirements (as specified in the Intel® 80333 I/O Processor
Design Guide) for these two power rails.
No
Fix. Not to be fixed. See the
Fix. Not to be fixed. See the
32
for specifics on PWRDELAY. Signals not included are DDR, PCI-Express and
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Intel® 80333 I/O Processor
7.
7.
Non-Core Errata
17