SAA7144 NXP Semiconductors, SAA7144 Datasheet - Page 12

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SAA7144

Manufacturer Part Number
SAA7144
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SAA7144

Package Type
LQFP
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SAA7144HL
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Part Number:
SAA7144HL/V1
Manufacturer:
MITSUBISHI
Quantity:
1 000
Philips Semiconductors
9397 750 14454
Product data sheet
8.3 Chrominance processing
The 9-bit chrominance signal is fed to the multiplication inputs of a quadrature
demodulator, where two subcarrier signals from the local oscillator DTO are applied
(0 and 90 phase relationship to the demodulator axis). The frequency is dependent on
the present color standard.
The output signals of the multipliers are low-pass filtered (four programmable
characteristics) to achieve the desired bandwidth for the color difference signals (PAL,
NTSC) or the 0 and 90 FM signals (SECAM).
The color difference signals are fed to the Brightness Contrast Saturation (BCS) block,
which contains the following five functions:
Fig 8. Clamp and gain flow.
AGC (automatic gain control for chrominance PAL and NTSC)
Chrominance amplitude matching (different gain factors for (R
achieve CCIR-601 levels C
Chrominance saturation control
Luminance contrast and brightness
Limiting Y-C
requirements.
NO BLANKING ACTIVE
CLAMP
WIPE = white peak level (254).
SBOT = sync bottom level (1).
CLL = clamp level [60 Y (128 C)].
HSY = horizontal sync pulse.
HCL = horizontal clamp pulse.
1
CLL
B
-C
R
CLAMP
to the values 1 (minimum) and 254 (maximum) to fulfil CCIR-601
0
1
Rev. 01 — 21 April 2005
HCL
<- CLAMP
NO CLAMP
ANALOG INPUT
1
R
0
and C
VBLK
ADC
B
0
for all standards)
GAIN
0
SBOT
GAIN ->
1
Quadruple video input processor
1
GAIN
HSY
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
fast
0
SAA7144HL
GAIN
1
Y) and (B
WIPE
slow
0
mgc647
GAIN
Y) to
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