SAA7113H NXP Semiconductors, SAA7113H Datasheet - Page 23

• Manufacturer Part Number: SAA7113H
• Manufacturer: NXP Semiconductors

Specifications of SAA7113H

• Video Resolution (max): 720Pixels
• Pin Count: 44
• Package Type: PQFP
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
9397 750 14232
Product data sheet
8.8 Multistandard VBI data slicer
Table 5:
The multistandard data slicer is a Vertical Blanking Interval (VBI) and Full Field (FF) video
data acquisition block. In combination with software modules the slicer acquires most
existing formats of broadcast VBI and FF data.
The implementation and programming model of the multistandard VBI data slicer is similar
to the text slicer built in the SAA5284 (Multimedia video data acquisition circuit).
The circuitry recovers the actual clock phase during the clock run-in period, slices the data
bits with the selected data rate, and groups them into bytes. The clock frequency, signal
source, field frequency and accepted error count must be defined via the I
subaddress 40h, bits 7 to 4.
Several standards can be selected per VBI line. The supported VBI data standards are
described in
The programming of the desired standards is done via I
(LCR2[7:0] to LCR24[7:0]); see detailed description in
processing to the signals source, there are offsets in horizontal and vertical direction
available via the I
(VOFF[8]) and 5Ah (VOFF[7:0]). The formatting of the decoded VBI data is done within
the output interface to the VPO-bus. For a detailed description of the sliced data format
see
Table 6:
Internal power-on
control sequence
Directly after power-on
asynchronous reset
Synchronous reset
sequence
Status after power-on
control sequence
Standard type
Teletext EuroWST, CCST
European closed caption
VPS
Wide screen signalling bits
US teletext (WST)
US closed caption (line 21)
Teletext
VITC/EBU time codes (Europe)
VITC/SMPTE time codes (USA)
Table
20.
Power-on control sequence
Supported VBI standards
Table
2
C-bus in subaddresses 5Bh (HOFF[10:8]), 59h (HOFF[7:0]) and 5Bh
6.
Pin output status
VPO7 to VPO0, RTCO, RTS0, RTS1, SDA
and LLC are in high-impedance state
LLC and SDA become active; VPO7 to
VPO0, RTCO, RTS0 and RTS1 are held in
high-impedance state
VPO7 to VPO0, RTCO, RTS0 and RTS1
are held in high-impedance state
Rev. 02 — 9 May 2005
Data rate
(Mbit/s)
6.9375
0.500
5
5
5.7272
0.503
6.9375
1.8125
1.7898
Framing code
27h
001
9951h
1E3C1Fh
27h
001
programmable
programmable
programmable
Section
2
C-bus subaddresses 41h to 57h
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
9-bit video input processor
8.10. To adjust the slicers
Remarks
direct switching to
high-impedance for 20 ms to
200 ms
internal reset sequence
after power-on (reset
sequence) a complete
I
required
2
C-bus transmission is
FC window Hamming
WST625
CC625
VPS
WSS
WST525
CC525
general text optional
VITC625
VITC625
SAA7113H
2
C-bus in
check
always
always
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