SAA7113H NXP Semiconductors, SAA7113H Datasheet - Page 41

• Manufacturer Part Number: SAA7113H
• Manufacturer: NXP Semiconductors

Specifications of SAA7113H

• Video Resolution (max): 720Pixels
• Pin Count: 44
• Package Type: PQFP
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
9397 750 14232
Product data sheet
9.2.10 Subaddress 09h
9.2.9 Subaddress 08h
Table 36:
Table 37:
Function
Vertical noise reduction (VNOI)
Normal mode (recommended setting)
Fast mode [applicable for stable sources only; Automatic
Field Detection (AUFD) must be disabled]
Free running mode
Vertical noise reduction bypassed
Horizontal PLL (HPLL)
PLL closed
PLL open; horizontal frequency fixed
Horizontal time constant selection (HTC1 and HTC0)
TV mode (recommended for poor quality TV signals only;
do not use for new applications)
VTR mode (recommended if a deflection control circuit is
directly connected to SAA7113H)
Reserved
Fast locking mode (recommended setting)
Forced ODD/EVEN toggle FOET
ODD/EVEN signal toggles only with interlaced source
ODD/EVEN signal toggles fieldwise even if source is
non-interlaced
Field selection (FSEL)
50 Hz, 625 lines
60 Hz, 525 lines
Automatic field detection (AUFD)
Field state directly controlled via FSEL
Automatic field detection
Function
Aperture factor (APER); see
Aperture factor = 0
Aperture factor = 0.25
Sync control subaddress 08h (D7 to D5, D3 to D0)
Luminance control subaddress 09h (D7 to D0)
Rev. 02 — 9 May 2005
Figure 11
to
Figure 18
Control bit
APER1
APER0
APER1
APER0
Control bit Logic level Data bit
VNOI1
VNOI0
VNOI1
VNOI0
VNOI1
VNOI0
VNOI1
VNOI0
HPLL
HPLL
HTC1 and
HTC0
HTC1 and
HTC0
HTC1 and
HTC0
HTC1 and
HTC0
FOET
FOET
FSEL
FSEL
AUFD
AUFD
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
9-bit video input processor
0
0
0
1
1
0
1
1
0
1
00
01
10
11
0
1
0
1
0
1
Logic level Data bit
0
0
0
1
SAA7113H
D1
D0
D1
D0
D1
D0
D1
D0
D2
D2
D4 and D3
D4 and D3
D4 and D3
D4 and D3
D5
D5
D6
D6
D7
D7
D1
D0
D1
D0
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