AT94K10AL-25DQC Atmel, AT94K10AL-25DQC Datasheet - Page 30
AT94K10AL-25DQC
Manufacturer Part Number
AT94K10AL-25DQC
Description
Manufacturer
Atmel
Datasheet
1.AT94K10AL-25DQC.pdf
(204 pages)
Specifications of AT94K10AL-25DQC
Device System Gates
10000
Propagation Delay Time
12.7ns
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temperature Classification
Commercial
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / RoHS Status
Not Compliant
Available stocks
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Price
Part Number:
AT94K10AL-25DQC
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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3.7
3.7.1
3.7.2
30
System Control
AT94KAL Series FPSLIC
Configuration Modes
System Control Register – FPGA/AVR
The AT94K family has four configuration modes controlled by mode pins M0 and M2, see
3-6.
Table 3-6.
Modes 2 and 3 are reserved and are used for factory test.
Modes 0 and 1 are pin-compatible with the appropriate AT40K counterpart. AVR I/O will be
taken over by the configuration logic for the CHECK pin during both modes.
Refer to the “AT94K Series Configuration” application note for details on downloading
bitstreams.
The configuration control register in the FPSLIC consists of 8 bytes of data, which are loaded
with the FPGA/Prog. Code at power-up from external nonvolatile memory. FPSLIC System Con-
trol Register values, see
defaults are included in the software.
Table 3-7.
M2
0
0
1
1
Bit
SCR0 - SCR1
SCR2
SCR3
SCR4
Configuration Modes
FPSLIC System Control Register
Description
Reserved
0 = Enable Cascading
1 = Disable Cascading
SCR2 controls the operation of the dual-function I/O CSOUT. When SCR2 is set,
the CSOUT pin is not used by the configuration during downloads, set this bit for
configurations where two or more devices are cascaded together. This applies for
configuration to another FPSLIC device or to an FPGA.
0 = Check Function Enabled
1 = Check Function Disabled
SCR3 controls the operation of the CHECK pin and enables the Check Function.
When SCR3 is set, the dual use AVR I/O/CHECK pin is not used by the
configuration during downloads, and can be used as AVR I/O.
0 = Memory Lockout Disabled
1 = Memory Lockout Enabled
SCR4 is the Security Flag and controls the writing and checking of configuration
memory during any subsequent configuration download. When SCR4 is set, any
subsequent configuration download initiated by the user, whether a normal
download or a CHECK function download, causes the INIT pin to immediately
activate. CON is released, and no further configuration activity takes place. The
download sequence during which SCR4 is set is NOT affected. The Control
Register write is also prohibited, so bit SCR4 may only be cleared by a power-on
reset or manual reset.
M0
0
1
0
1
Table
3-7, can be set in the System Designer software. Recommended
Name
Mode 0 - Master Serial
Mode 1 - Slave Serial Cascade
Mode 2 - Reserved
Mode 3 - Reserved
1138I–FPSLI–1/08
Table
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