AT94K10AL-25DQC Atmel, AT94K10AL-25DQC Datasheet - Page 46

• Manufacturer Part Number: AT94K10AL-25DQC
• Manufacturer: Atmel

Specifications of AT94K10AL-25DQC

• Device System Gates: 10000
• Propagation Delay Time: 12.7ns
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / RoHS Status: Not Compliant

Data Direct
A 16-bit data address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the
destination or source register.
Data Indirect with Displacement
Operand address is the result of the Y- or Z-register contents added to the address contained in
6 bits of the instruction word.
Data Indirect
Operand address is the contents of the X-, Y- or the Z-register.
Data Indirect with Pre-decrement
The X-, Y- or the Z-register is decremented before the operation. Operand address is the decre-
mented contents of the X, Y or the Z-register.
Data Indirect with Post-increment
The X-, Y- or the Z-register is incremented after the operation. The operand address is the con-
tent of the X-, Y- or the Z-register prior to incrementing.
Direct Program Address, JMP and CALL
Program execution continues at the address immediate in the instruction words.
Indirect Program Addressing, IJMP and ICALL
Program execution continues at address contained by the Z-register (i.e., the PC is loaded with
the contents of the Z-register).
Relative Program Addressing, RJMP and RCALL
Program execution continues at address PC + k + 1. The relative address k is -2048 to 2047.
4.10.2
Memory Access Times and Instruction Execution Timing
This section describes the general access timing concepts for instruction execution and internal
memory access.
The AVR CPU is driven by the XTAL1 input directly generated from the external clock crystal for
the chip. No internal clock division is used.
Figure 4-6
shows the parallel instruction fetches and instruction executions enabled by the Har-
vard architecture and the fast-access register file concept. This is the basic pipelining concept to
obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, func-
tions per clocks and functions per power-unit.
AT94KAL Series FPSLIC
46
1138I–FPSLI–1/08