CBTU4411EE-T NXP Semiconductors, CBTU4411EE-T Datasheet
CBTU4411EE-T
Specifications of CBTU4411EE-T
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CBTU4411EE-T Summary of contents
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CBTU4411 11-bit DDR2 SDRAM MUX/bus switch with 12 Rev. 03 — 12 October 2009 1. General description This 11-bit bus switch is designed for 1 1 input levels. Each Host port pin (HPn) is multiplexed to ...
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... ESD protection exceeds 1500 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 750 V CDM per JESD22-C101 3. Ordering information Table +85 C. amb Type number CBTU4411EE CBTU4411_3 Product data sheet 11-bit DDR2 SDRAM MUX/bus switch with 12 ON-resistance pull-down resistors on xDPn port Ordering information Package ...
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... NXP Semiconductors 4. Functional diagram VREF TERM STREN (1) Selectable. Fig 1. HPn A from switch control Fig 2. CBTU4411_3 Product data sheet 11-bit DDR2 SDRAM MUX/bus switch with 12 HP0 HP10 (1) ( (1) ( CONTROL Functional diagram (positive logic xDPn SWITCH 400 VBIAS 002aae848 Simplified schematic, channel 0 to channel 9 Rev. 03 — ...
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... HP7 3DP8 2DP8 1DP8 3DP7 2DP7 Blank cell indicates no ball at that location. Ball mapping (transparent top view) Rev. 03 — 12 October 2009 CBTU4411 CBTU4411EE 002aae837 Transparent top view 2DP0 1DP1 2DP1 3DP1 0DP2 3DP0 0DP1 HP1 GND 0DP3 2DP3 2DP4 1DP5 ...
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... NXP Semiconductors 5.2 Pin description Table 2. Symbol HP0 to HP10 EN STREN S0 S1 VREF VBIAS TERM 0DP0, 1DP0, 2DP0, 3DP0 0DP1, 1DP1, 2DP1, 3DP1 0DP2, 1DP2, 2DP2, 3DP2 0DP3, 1DP3, 2DP3, 3DP3 0DP4, 1DP4, 2DP4, 3DP4 0DP5, 1DP5, 2DP5, 3DP5 0DP6, 1DP6, 2DP6, 3DP6 ...
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... NXP Semiconductors 6. Functional description Refer to 6.1 Function selection Table 3. Function selection, channel 0 to channel HIGH voltage level LOW voltage level; high-Z = high-impedance Don’t care. Inputs HPn high high high high-Z CBTU4411_3 Product data sheet 11-bit DDR2 SDRAM MUX/bus switch with 12 Figure 1 “ ...
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Table 4. Function selection, channel HIGH voltage level LOW voltage level; high-Z = high-impedance Don’t care. Inputs 0DP10 STREN HP10 VBIAS high ...
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... NXP Semiconductors 7. Limiting values Table 6. In accordance with the Absolute Maximum Rating System (IEC 60134). The package thermal impedance is calculated in accordance with JESD 51. Symbol stg [1] The input and output negative voltage ratings may be exceeded if the input and output clamping current ratings are observed. ...
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... NXP Semiconductors 9. Static characteristics Table 8. Static characteristics +85 C amb Symbol Parameter V input clamping voltage IK V termination voltage T V pull-up voltage pu I input leakage current LI I supply current DD C input capacitance in C switch on capacitance resistance resistance ON mismatch between channels R pull-down resistance pd R pull-up resistance ...
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... NXP Semiconductors Fig 6. 10. Dynamic characteristics Table 9. Dynamic characteristics V = 1 Symbol Parameter t propagation delay PD t driver enable delay to HIGH level PZH t driver enable delay to LOW level PZL t driver disable delay from HIGH level from Sn to HPn or xDPn PHZ t driver disable delay from LOW level from Sn to HPn or xDPn ...
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... NXP Semiconductors 11. HPn to xDPn AC waveforms and test circuit Fig 7. (1) See (2) Waveform 1 is for an output with internal conditions such that the output is HIGH except when Fig 8. Fig 9. CBTU4411_3 Product data sheet 11-bit DDR2 SDRAM MUX/bus switch with 12 input 0 PLH output Input to output propagation delays ...
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... NXP Semiconductors 12. xDPn to HPn AC waveforms and test circuit (1) See (2) Waveform 1 is for an output with internal conditions such that the output is LOW except when (3) Waveform 2 is for an output with internal conditions such that the output is HIGH except when Fig 10. 3-state output enable and disable times Fig 11 ...
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... NXP Semiconductors Fig 13. Test circuit (xDPn to HPn) 13. Test information Table 10. Condition bias V < 0.5V bias CBTU4411_3 Product data sheet 11-bit DDR2 SDRAM MUX/bus switch with HPn 2.54 cm (1") SSTL_18 driver All input pulses are supplied by generators having the following characteristics: PRR 10 MHz ...
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... NXP Semiconductors 14. Package outline LFBGA72: plastic low profile fine-pitch ball grid array package; 72 balls; body 1.05 mm ball A1 index area ball A1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.3 1.20 0.35 mm 1.5 0.2 0.95 0.25 OUTLINE VERSION IEC SOT856-1 Fig 14. Package outline SOT856-1 (LFBGA72) ...
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... NXP Semiconductors 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 15.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 15.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 15. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 16. Abbreviations Table 13. Acronym CDM DDR2 DIMM DQM ESD HBM LVCMOS MM MUX PRR RC SDRAM SSTL_18 ...
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... CBTU4411_3 20091012 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section 2 667 Mbit/s, 200 MHz to 333 MHz DDR2 data bus” to “Suitable to be used with 400 Mbit/s to 800 Mbit/s, 200 MHz to 400 MHz DDR2 data bus” ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 6 6.1 Function selection Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 10 11 HPn to xDPn AC waveforms and test circuit . 11 12 xDPn to HPn AC waveforms and test circuit ...