CBTU4411EE-T NXP Semiconductors, CBTU4411EE-T Datasheet - Page 5

• Manufacturer Part Number: CBTU4411EE-T
• Manufacturer: NXP Semiconductors

Specifications of CBTU4411EE-T

• Operating Temperature (max): 85C
• Operating Temperature (min): 0C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
CBTU4411_3
Product data sheet
5.2 Pin description
Table 2.
Symbol
HP0 to HP10
EN
STREN
S0
S1
VREF
VBIAS
TERM
0DP0, 1DP0,
2DP0, 3DP0
0DP1, 1DP1,
2DP1, 3DP1
0DP2, 1DP2,
2DP2, 3DP2
0DP3, 1DP3,
2DP3, 3DP3
0DP4, 1DP4,
2DP4, 3DP4
0DP5, 1DP5,
2DP5, 3DP5
0DP6, 1DP6,
2DP6, 3DP6
0DP7, 1DP7,
2DP7, 3DP7
0DP8, 1DP8,
2DP8, 3DP8
0DP9, 1DP9,
2DP9, 3DP9
0DP10, 1DP10,
2DP10, 3DP10
GND
V
DD
Pin description
Pin
B5, B8, B10, D10,
G10, K10, K8, K5,
K3, J2, F2
C2
A2
B2
A1
C1
D1
B1
A4, A5,
A6, B6
B7, A7,
A8, A9
A10, A11,
B11, C11
C10, D11,
E10, E11
F11, G11,
H10, H11
J11, J10,
K11, L11
K9, L9,
L8, L7
K6, L6,
L5, L4
K4, L3,
L2, L1
K1, J1,
H2, H1
G1, F1,
E1, E2
B4, B9, D2, F10,
G2, K2, K7
A3, B3, L10
Rev. 03 — 12 October 2009
11-bit DDR2 SDRAM MUX/bus switch with 12
Description
Host ports
LVCMOS level enable input (active LOW). When connected
HIGH, all DIMM ports will be disconnected (show a
high-impedance path) from the Host ports.
Strobe enable. LVCMOS level strobe enable input
(active HIGH). When tied LOW, channel 10 (HP10 and its
DP ports) functions identically to all other channels. When
tied HIGH, channel 10 is designated as the Strobe channel
(see
Figure
Select inputs; type SSTL_18. See
selection”.
Reference voltage for the pseudo-differential SSTL_18
select inputs (S0, S1).
Voltage bias for the DIMM port pull-down resistor (R
LVCMOS level input pin activates termination resistance on
Sn inputs when HIGH; high-impedance when LOW.
DIMM port 0
DIMM port 1
DIMM port 2
DIMM port 3
DIMM port 4
DIMM port 5
DIMM port 6
DIMM port 7
DIMM port 8
DIMM port 9
DIMM port 10
Ground
Positive supply voltage
Section 6.1 “Function
3).
selection”,
Section 6.1 “Function
CBTU4411
Figure 2
© NXP B.V. 2009. All rights reserved.
ON resistance
and
pd
).
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