UJA1065TW/3V3 NXP Semiconductors, UJA1065TW/3V3 Datasheet - Page 5

• Manufacturer Part Number: UJA1065TW/3V3
• Description: Network Controller & Processor ICs HI SPEED CAN SYSTEM
• Manufacturer: NXP Semiconductors

Specifications of UJA1065TW/3V3

• Number Of Transceivers: 1
• Power Down Mode: Standby
• Operating Supply Voltage (min): 5.5V
• Supply Current: 10mA
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Product: Controller Area Network (CAN)
• Data Rate: 20 Kbps
• Supply Voltage (max): 27 V, 52 V
• Supply Voltage (min): 5.5 V
• Supply Current (max): 10 mA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: HTSSOP EP
• Lead Free Status / RoHS Status: Compliant
• Other names: UJA1065TW/3V3,512

NXP Semiconductors
5. Pinning information
UJA1065_7
Product data sheet
5.1 Pinning
5.2 Pin description
Table 2.
Symbol
n.c.
n.c.
TXDL
V1
RXDL
RSTN
INTN
EN
SDI
SDO
SCK
SCS
TXDC
RXDC
n.c.
TEST
Fig 2.
Pin configuration
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
not connected
not connected
LIN transmit data input (LOW for dominant, HIGH for recessive)
voltage regulator output for the microcontroller (3.3 V or 5 V depending on the
SBC version)
LIN receive data output (LOW when dominant, HIGH when recessive)
reset output to microcontroller (active LOW; will detect clamping situations)
interrupt output to microcontroller (active LOW; open-drain, wire-AND this pin to
other ECU interrupt outputs)
enable output (active HIGH; push-pull, LOW with every reset/watchdog
overflow)
SPI data input
SPI data output (floating when pin SCS is HIGH)
SPI clock input
SPI chip select input (active LOW)
CAN transmit data input (LOW for dominant; HIGH for recessive)
CAN receive data output (LOW when dominant; HIGH when recessive)
not connected
test pin (should be connected to ground in application)
Rev. 07 — 25 February 2010
RXDC
RSTN
TXDC
RXDL
TXDL
TEST
INTN
SDO
SCK
SCS
n.c.
n.c.
SDI
n.c.
EN
V1
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
High-speed CAN/LIN fail-safe system basis chip
UJA1065TW
001aac306
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
BAT42
SENSE
V3
SYSINH
n.c.
BAT14
RTLIN
LIN
SPLIT
GND
CANL
CANH
V2
n.c.
WAKE
INH/LIMP
UJA1065
© NXP B.V. 2010. All rights reserved.
5 of 76