IDT82V3380PF8 IDT, Integrated Device Technology Inc, IDT82V3380PF8 Datasheet - Page 35

• Manufacturer Part Number: IDT82V3380PF8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V3380PF8

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

phase locked to any input clock. The frequency offset acquiring method
is selected by the MAN_HOLDOVER bit, the AUTO_AVG bit and the
FAST_AVG bit, as shown in
Table 19: Frequency Offset Control in Holdover Mode
3.10.1.5.1 Automatic Instantaneous
when it enters Holdover mode. The accuracy is 4.4X10
3.10.1.5.2 Automatic Slow Averaged
employed to get the frequency offset. The IIR filter gives a 3 dB attenua-
tion point corresponding to a period of 110 minutes. The accuracy is
1.1X10
3.10.1.5.3 Automatic Fast Averaged
employed to get the frequency offset. The IIR filter gives a 3 dB attenua-
tion point corresponding to a period of 8 minutes. The accuracy is
1.1X10
3.10.1.5.4 Manual
T0_HOLDOVER_FREQ[23:0] bits. The accuracy is 1.1X10
CURRENT_DPLL_FREQ[23:0] bits.
T0_HOLDOVER_FREQ[23:0] bits. The value to be written can refer to
the value read from the CURRENT_DPLL_FREQ[23:0] bits or the
T0_HOLDOVER_FREQ[23:0] bits (refer to
Frequency Offset
tering.
3.10.1.5.5 Holdover Frequency Offset Read
Automatic Fast Averaged and is set by related register bits, can be read
from the T0_HOLDOVER_FREQ[23:0] bits by setting the READ_AVG
bit and the FAST_AVG bit, as shown in
Functional Description
IDT82V3380
By this method, the T0 DPLL freezes at the operating frequency
By this method, an internal IIR (Infinite Impulse Response) filter is
By this method, an internal IIR (Infinite Impulse Response) filter is
By this method, the frequency offset is set by the
The frequency offset of the T0 DPLL output is indicated by the
The device provides a reference for the value to be written to the
The offset value, which is acquired by Automatic Slow Averaged,
MAN_HOLDOVER
-5
-5
ppm.
ppm.
0
1
Read); or then be processed by external software fil-
Table
19:
AUTO_AVG
Table
0
1
Chapter 3.10.1.5.5 Holdover
20.
don’t-care
-8
ppm.
-5
ppm.
FAST_AVG
don’t-care
0
1
35
Table 20: Holdover Frequency Offset Read
3.10.1.6
selected input clock.
3.10.2
3.10.2.1
and is affected by any input clock. The accuracy of the T4 DPLL output
is equal to that of the master clock.
3.10.2.2
DPLL.
offset of the T4 DPLL output track those of the T4 selected input clock;
when unlocked, the phase and frequency offset of the T4 DPLL output
attempt to track those of the selected input clock.
damping factor are set by the T4_DPLL_LOCKED_BW[1:0] bits and the
T4_DPLL_LOCKED_DAMPING[2:0] bits respectively.
3.10.2.3
acquired in Locked mode to control its output. The T4 DPLL output is not
READ_AVG FAST_AVG
The frequency offset in ppm is calculated as follows:
In Pre-Locked2 mode, the T0 DPLL output attempts to track the
The Pre-Locked2 mode is a secondary, temporary mode.
The T4 path is simpler compared with the T0 path.
In Free-Run mode, the T4 DPLL output refers to the master clock
In Locked mode, the T4 selected input clock may be locked in the T4
When the T4 selected input clock is locked, the phase and frequency
The T4 DPLL loop is closed in Locked mode. Its bandwidth and
In Holdover mode, the T4 DPLL resorts to the stored frequency data
0
1
Holdover Frequency Offset (ppm) = T0_HOLDOVER_FREQ[23:0] X
0.000011
Pre-Locked2 Mode
T4 DPLL OPERATING MODE
Free-Run Mode
Locked Mode
Holdover Mode
don’t-care The value is equal to the one written to.
0
1
Frequency Offset Acquiring Method
The value is acquired by Automatic Slow Averaged
method, not equal to the one written to.
The value is acquired by Automatic Fast Averaged
method, not equal to the one written to.
SYNCHRONOUS ETHERNET WAN PLL
Automatic Slow Averaged
Automatic Fast Averaged
Automatic Instantaneous
T0_HOLDOVER_FREQ[23:0]
Manual
Offset Value Read from
October 20, 2008